Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 019791/0092 | |
| Pages: | 3 |
| | Recorded: | 08/30/2007 | | |
| Attorney Dkt #: | 69804-055 |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
1
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Patent #:
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Issue Dt:
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10/02/2007
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Application #:
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11024470
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Filing Dt:
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12/30/2004
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Publication #:
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Pub Dt:
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07/07/2005
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Title:
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DESIGN METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT SUPPRESSING POWER SUPPLY NOISE
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Assignee
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| 1006, OAZA KADOMA |
| KADOMA-SHI, OSAKA 571-8501, JAPAN |
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Correspondence name and address
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MCDERMOTT WILL & EMERY LLP
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600 13TH STREET, NW
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WASHINGTON, DC 20005-3096
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