Total properties:
13
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Patent #:
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NONE
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Issue Dt:
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Application #:
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11424076
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Filing Dt:
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06/14/2006
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Publication #:
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Pub Dt:
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12/20/2007
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Title:
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SEMICONDUCTOR STRUCTURE INCLUDING ISOLATION REGION WITH VARIABLE LINEWIDTH AND METHOD FOR FABRICATION THEROF
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Patent #:
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Issue Dt:
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11/10/2009
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Application #:
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11739595
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Filing Dt:
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04/24/2007
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Publication #:
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Pub Dt:
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10/30/2008
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Title:
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INTEGRATED CIRCUIT MANUFACTURING METHOD USING HARD MASK
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Patent #:
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NONE
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Issue Dt:
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Application #:
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11837161
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Filing Dt:
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08/10/2007
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Publication #:
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Pub Dt:
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02/12/2009
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Title:
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MOSFET WITH METAL GATE ELECTRODE
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Patent #:
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NONE
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Issue Dt:
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Application #:
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11845448
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Filing Dt:
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08/27/2007
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Publication #:
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Pub Dt:
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03/05/2009
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Title:
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SPACER UNDERCUT FILLER, METHOD OF MANUFACTURE THEREOF AND ARTICLES COMPRISING THE SAME
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Patent #:
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Issue Dt:
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11/24/2015
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Application #:
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11851269
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Filing Dt:
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09/06/2007
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Publication #:
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Pub Dt:
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03/12/2009
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Title:
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Plasma Vapor Deposition
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Patent #:
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Issue Dt:
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06/12/2012
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Application #:
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11852910
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Filing Dt:
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09/10/2007
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Publication #:
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Pub Dt:
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03/12/2009
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Title:
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ELECTRO CHEMICAL DEPOSITION SYSTEMS AND METHODS OF MANUFACTURING USING THE SAME
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Patent #:
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Issue Dt:
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02/23/2010
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Application #:
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11855887
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Filing Dt:
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09/14/2007
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Publication #:
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Pub Dt:
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03/19/2009
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Title:
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SYSTEM AND METHOD FOR SEMICONDUCTOR DEVICE FABRICATION USING MODELING
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Patent #:
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Issue Dt:
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08/31/2010
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Application #:
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11860955
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Filing Dt:
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09/25/2007
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Publication #:
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Pub Dt:
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03/26/2009
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Title:
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INTEGRATED CIRCUITS AND METHODS OF DESIGN AND MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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11/15/2011
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Application #:
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11861478
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Filing Dt:
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09/26/2007
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Publication #:
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Pub Dt:
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03/26/2009
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Title:
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METHODS OF PATTERNING INSULATING LAYERS USING ETCHING TECHNIQUES THAT COMPENSATE FOR ETCH RATE VARIATIONS
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Patent #:
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NONE
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Issue Dt:
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Application #:
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11868362
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Filing Dt:
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10/05/2007
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Publication #:
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Pub Dt:
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04/09/2009
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Title:
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Lithography Systems and Methods of Manufacturing Using Thereof
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Patent #:
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Issue Dt:
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05/06/2014
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Application #:
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11868374
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Filing Dt:
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10/05/2007
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Publication #:
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Pub Dt:
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04/09/2009
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Title:
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Lithography Systems and Methods of Manufacturing Using Thereof
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Patent #:
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Issue Dt:
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06/29/2010
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Application #:
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11872298
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Filing Dt:
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10/15/2007
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Publication #:
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Pub Dt:
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04/16/2009
| | | | |
Title:
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METHOD FOR FABRICATING A SEMICONDUCTOR GATE STRUCTURE
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|
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Patent #:
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Issue Dt:
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04/12/2011
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Application #:
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11874118
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Filing Dt:
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10/17/2007
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Publication #:
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Pub Dt:
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04/23/2009
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Title:
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METHODS OF FORMING FIELD EFFECT TRANSISTORS HAVING STRESS-INDUCING SIDEWALL INSULATING SPACERS THEREON
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