skip navigationU S P T O SealUnited States Patent and Trademark Office AOTW logo
Home|Site Index|Search|Guides|Contacts|eBusiness|eBiz alerts|News|Help
Assignments on the Web > Patent Query
Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:020130/0145   Pages: 5
Recorded: 11/19/2007
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 13
1
Patent #:
NONE
Issue Dt:
Application #:
11424076
Filing Dt:
06/14/2006
Publication #:
Pub Dt:
12/20/2007
Title:
SEMICONDUCTOR STRUCTURE INCLUDING ISOLATION REGION WITH VARIABLE LINEWIDTH AND METHOD FOR FABRICATION THEROF
2
Patent #:
Issue Dt:
11/10/2009
Application #:
11739595
Filing Dt:
04/24/2007
Publication #:
Pub Dt:
10/30/2008
Title:
INTEGRATED CIRCUIT MANUFACTURING METHOD USING HARD MASK
3
Patent #:
NONE
Issue Dt:
Application #:
11837161
Filing Dt:
08/10/2007
Publication #:
Pub Dt:
02/12/2009
Title:
MOSFET WITH METAL GATE ELECTRODE
4
Patent #:
NONE
Issue Dt:
Application #:
11845448
Filing Dt:
08/27/2007
Publication #:
Pub Dt:
03/05/2009
Title:
SPACER UNDERCUT FILLER, METHOD OF MANUFACTURE THEREOF AND ARTICLES COMPRISING THE SAME
5
Patent #:
Issue Dt:
11/24/2015
Application #:
11851269
Filing Dt:
09/06/2007
Publication #:
Pub Dt:
03/12/2009
Title:
Plasma Vapor Deposition
6
Patent #:
Issue Dt:
06/12/2012
Application #:
11852910
Filing Dt:
09/10/2007
Publication #:
Pub Dt:
03/12/2009
Title:
ELECTRO CHEMICAL DEPOSITION SYSTEMS AND METHODS OF MANUFACTURING USING THE SAME
7
Patent #:
Issue Dt:
02/23/2010
Application #:
11855887
Filing Dt:
09/14/2007
Publication #:
Pub Dt:
03/19/2009
Title:
SYSTEM AND METHOD FOR SEMICONDUCTOR DEVICE FABRICATION USING MODELING
8
Patent #:
Issue Dt:
08/31/2010
Application #:
11860955
Filing Dt:
09/25/2007
Publication #:
Pub Dt:
03/26/2009
Title:
INTEGRATED CIRCUITS AND METHODS OF DESIGN AND MANUFACTURE THEREOF
9
Patent #:
Issue Dt:
11/15/2011
Application #:
11861478
Filing Dt:
09/26/2007
Publication #:
Pub Dt:
03/26/2009
Title:
METHODS OF PATTERNING INSULATING LAYERS USING ETCHING TECHNIQUES THAT COMPENSATE FOR ETCH RATE VARIATIONS
10
Patent #:
NONE
Issue Dt:
Application #:
11868362
Filing Dt:
10/05/2007
Publication #:
Pub Dt:
04/09/2009
Title:
Lithography Systems and Methods of Manufacturing Using Thereof
11
Patent #:
Issue Dt:
05/06/2014
Application #:
11868374
Filing Dt:
10/05/2007
Publication #:
Pub Dt:
04/09/2009
Title:
Lithography Systems and Methods of Manufacturing Using Thereof
12
Patent #:
Issue Dt:
06/29/2010
Application #:
11872298
Filing Dt:
10/15/2007
Publication #:
Pub Dt:
04/16/2009
Title:
METHOD FOR FABRICATING A SEMICONDUCTOR GATE STRUCTURE
13
Patent #:
Issue Dt:
04/12/2011
Application #:
11874118
Filing Dt:
10/17/2007
Publication #:
Pub Dt:
04/23/2009
Title:
METHODS OF FORMING FIELD EFFECT TRANSISTORS HAVING STRESS-INDUCING SIDEWALL INSULATING SPACERS THEREON
Assignor
1
Exec Dt:
11/19/2007
Assignee
1
AM CAMPEON 1-12
NEUBIBERG, GERMANY 85579
Correspondence name and address
HEATHER ROWLAND
4505 EMPEROR BLVD., SUITE 310
DURHAM, NC 27703

Search Results as of: 05/11/2024 05:39 PM
If you have any comments or questions concerning the data displayed, contact PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified: August 25, 2017 v.2.6
| .HOME | INDEX| SEARCH | eBUSINESS | CONTACT US | PRIVACY STATEMENT