Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 020316/0501 | |
| Pages: | 10 |
| | Recorded: | 12/28/2007 | | |
| Conveyance: | SECURITY INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
4
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Patent #:
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NONE
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Issue Dt:
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Application #:
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11315892
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Filing Dt:
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12/22/2005
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Publication #:
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Pub Dt:
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09/07/2006
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Title:
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Systems for performing parallel distributed processing for physical layout generation
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Patent #:
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Issue Dt:
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05/20/2008
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Application #:
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11357823
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Filing Dt:
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02/17/2006
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Publication #:
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Pub Dt:
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08/23/2007
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Title:
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METHODS FOR TILING INTEGRATED CIRCUIT DESIGNS
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Patent #:
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NONE
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Issue Dt:
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Application #:
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11500727
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Filing Dt:
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08/07/2006
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Publication #:
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Pub Dt:
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08/30/2007
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Title:
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Method for accelerating the RC extraction in integrated circuit designs
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Patent #:
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NONE
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Issue Dt:
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Application #:
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11732384
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Filing Dt:
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04/02/2007
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Publication #:
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Pub Dt:
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10/02/2008
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Title:
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System and method for simultaneous optimization of multiple scenarios in an integrated circuit design
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Assignees
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| 2010 NORTH FIRST STREET |
| SAN JOSE, CALIFORNIA 95131 |
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| 2010 NORTH FIRST STREET |
| SAN JOSE, CALIFORNIA 95131 |
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Correspondence name and address
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RUSSELL D. POLLOCK, ESQ.
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FOUR EMBARCADERO CENTER
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SUITE 4000
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SAN FRANCISCO, CA 94111
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