skip navigationU S P T O SealUnited States Patent and Trademark Office AOTW logo
Home|Site Index|Search|Guides|Contacts|eBusiness|eBiz alerts|News|Help
Assignments on the Web > Patent Query
Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:020614/0361   Pages: 3
Recorded: 03/03/2008
Attorney Dkt #:MURA3005CIP/REF
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 1
1
Patent #:
NONE
Issue Dt:
Application #:
12007406
Filing Dt:
01/10/2008
Publication #:
Pub Dt:
06/19/2008
Title:
Method of manufacturing wafer level chip size package
Assignor
1
Exec Dt:
01/28/2008
Assignee
1
38-32, MINAMIMACHI 5-CHOME
FUCHU-SHI, TOKYO, JAPAN
Correspondence name and address
RICHARD E. FICHTER
BACON & THOMAS, PLLC
625 SLATERS LANE FOURTH FLOOR
ALEXANDRIA, VA 22314

Search Results as of: 05/15/2024 04:22 PM
If you have any comments or questions concerning the data displayed, contact PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified: August 25, 2017 v.2.6
| .HOME | INDEX| SEARCH | eBUSINESS | CONTACT US | PRIVACY STATEMENT