Patent Assignment Details
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For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 020705/0277 | |
| Pages: | 4 |
| | Recorded: | 03/26/2008 | | |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
1
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Patent #:
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Issue Dt:
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04/13/2010
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Application #:
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11942384
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Filing Dt:
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11/19/2007
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Publication #:
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Pub Dt:
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05/22/2008
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Title:
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METHOD AND PROGRAM FOR DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT, METHOD AND PROGRAM FOR SUPPORTING DESIGN OF SEMICONDUCTOR INTEGRATED CIRCUIT, AND METHOD AND PROGRAM FOR CALCULATING WIRING PARASITIC CAPACITANCE
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Assignee
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| 1006 OAZA KADOMA, KADOMA-SHI |
| OSAKA, JAPAN 571-8501 |
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Correspondence name and address
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KENJI KAMATA
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1130 CONNECTICUT AVE., N.W., SUITE 1100
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PANASONIC PATENT CENTER
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WASHINGTON, DC 20036
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