Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
|
| Reel/Frame: | 020808/0971 | |
| Pages: | 3 |
| | Recorded: | 04/17/2008 | | |
| Attorney Dkt #: | 2686-999 |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
|
|
Total properties:
3
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2001
|
Application #:
|
09240121
|
Filing Dt:
|
01/29/1999
|
|
Title:
|
SEGMENTED ARCHITECTURE FOR WAFER TEST & BURN-IN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/26/2002
|
Application #:
|
09307394
|
Filing Dt:
|
05/07/1999
|
|
Publication #:
|
|
Pub Dt:
|
01/10/2002
| | | | |
|
Title:
|
SEMICONDUCTOR WAFER TEST AND BURN-IN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/03/2001
|
Application #:
|
09454131
|
Filing Dt:
|
12/03/1999
|
|
Title:
|
FLEXIBLE WAFER LEVEL PROBE
|
|
|
Assignee
|
|
|
|
|
| MUSASHINO-SHI |
| TOKYO, JAPAN |
|
|
Correspondence name and address
|
| |
JOHN M. JANEWAY
|
| |
155 108TH AVE NE
|
| |
SUITE 350
|
| |
BELLEVUE, WA 98004
|
Search Results as of:
05/06/2024 11:50 PM
If you have any comments or questions concerning the data displayed,
contact
PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified:
August 25, 2017 v.2.6
| 
