Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 021617/0327 | |
| Pages: | 5 |
| | Recorded: | 10/02/2008 | | |
| Attorney Dkt #: | 0671.52594 |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
10
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Patent #:
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Issue Dt:
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04/21/1998
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Application #:
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08669272
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Filing Dt:
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05/29/1996
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Title:
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THIN FILM TRANSISTOR MATRIX DEVICE AND METHOD FOR FABRICATING THE SAME
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Patent #:
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Issue Dt:
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06/18/2002
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Application #:
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09005176
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Filing Dt:
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01/08/1998
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Publication #:
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Pub Dt:
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03/07/2002
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Title:
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THIN FILM TRANSISTOR MATRIX DEVICE AND METHOD FOR FABRICATING THE SAME
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Patent #:
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Issue Dt:
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10/02/2001
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Application #:
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09298775
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Filing Dt:
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04/22/1999
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Title:
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TFT SUBSTRATE WITH LOW CONTACT RESISTANCE AND DAMAGE RESISTANT TERMINALS
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Patent #:
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Issue Dt:
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01/21/2003
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Application #:
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09925666
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Filing Dt:
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08/09/2001
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Publication #:
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Pub Dt:
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01/03/2002
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Title:
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TFT SUBSTRATE WITH LOW CONTACT RESISTANCE AND DAMAGE RESISTANT TERMINALS
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Patent #:
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Issue Dt:
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07/27/2004
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Application #:
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10080108
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Filing Dt:
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02/21/2002
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Publication #:
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Pub Dt:
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07/04/2002
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Title:
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THIN FILM TRANSISTOR MATRIX DEVICE AND METHOD FOR FABRICATING THE SAME
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Patent #:
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Issue Dt:
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05/24/2005
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Application #:
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10292179
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Filing Dt:
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11/12/2002
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Publication #:
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Pub Dt:
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04/10/2003
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Title:
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ITO FILM CONTACT STRUCTURE, TFT SUBSTRATE AND MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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01/02/2007
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Application #:
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10419474
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Filing Dt:
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04/21/2003
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Title:
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TFT SUBSTRATE WITH LOW CONTACT RESISTANCE AND DAMAGE RESISTANT TERMINALS
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Patent #:
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Issue Dt:
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07/11/2006
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Application #:
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10660053
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Filing Dt:
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09/11/2003
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Publication #:
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Pub Dt:
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03/11/2004
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Title:
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THIN FILM TRANSISTOR MATRIX DEVICE
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Patent #:
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Issue Dt:
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04/25/2006
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Application #:
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10999405
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Filing Dt:
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11/30/2004
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Publication #:
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Pub Dt:
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05/05/2005
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Title:
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ITO FILM CONTACT STRUCTURE, TFT SUBSTRATE AND MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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08/18/2009
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Application #:
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11377754
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Filing Dt:
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03/16/2006
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Publication #:
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Pub Dt:
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07/27/2006
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Title:
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METHOD FOR FABRICATING A THIN FILM TRANSISTOR MATRIX DEVICE
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Assignee
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| 22-22, NAGAIKE-CHO, ABENO-KU |
| OSAKA-SHI |
| OSAKA, JAPAN 545-8522 |
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Correspondence name and address
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GREER, BURNS & CRAIN, LTD.
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300 SOUTH WACKER DRIVE
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SUITE 2500
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CHICAGO, IL 60606
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