Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 021744/0521 | |
| Pages: | 4 |
| | Recorded: | 10/28/2008 | | |
| Attorney Dkt #: | 1374.37370CC5 |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
7
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Patent #:
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Issue Dt:
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04/23/2002
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Application #:
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09356707
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Filing Dt:
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07/20/1999
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Title:
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PROCESS FOR MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
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Patent #:
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Issue Dt:
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10/01/2002
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Application #:
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10050562
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Filing Dt:
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01/18/2002
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Publication #:
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Pub Dt:
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05/16/2002
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Title:
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PROCESS FOR MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
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Patent #:
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Issue Dt:
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03/11/2003
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Application #:
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10222848
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Filing Dt:
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08/19/2002
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Publication #:
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Pub Dt:
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12/19/2002
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Title:
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PROCESS FOR MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
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Patent #:
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Issue Dt:
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10/05/2004
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Application #:
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10369716
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Filing Dt:
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02/21/2003
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Publication #:
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Pub Dt:
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08/14/2003
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Title:
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PROCESS FOR MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10760292
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Filing Dt:
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01/21/2004
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Publication #:
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Pub Dt:
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08/05/2004
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Title:
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Process for manufacturing semiconductor integrated circuit device
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Patent #:
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Issue Dt:
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03/31/2009
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Application #:
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11357181
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Filing Dt:
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02/21/2006
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Publication #:
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Pub Dt:
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06/29/2006
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Title:
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PROCESS FOR MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
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Patent #:
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Issue Dt:
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02/09/2010
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Application #:
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12127564
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Filing Dt:
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05/27/2008
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Publication #:
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Pub Dt:
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09/25/2008
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Title:
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PROCESS FOR MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
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Assignee
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| 6-2, OTEMACHI 2-CHOME |
| CHIYODA-KU |
| TOKYO, JAPAN |
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Correspondence name and address
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ANTONELLI, TERRY, STOUT & KRAUS, LLP
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1300 N. 17TH STREET
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SUITE 1800
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ARLINGTON, VA 22209
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