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Total properties:
41
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Patent #:
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Issue Dt:
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01/26/1993
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Application #:
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07773827
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Filing Dt:
|
10/09/1991
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Title:
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ARRAY LAYOUT STRUCTURE FOR IMPLEMENTING LARGE HIGH-DENSITY ADDRESS DECODERS FOR GATE ARRAY MEMORIES
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Patent #:
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Issue Dt:
|
10/31/1995
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Application #:
|
08082867
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Filing Dt:
|
06/29/1993
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Title:
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METHOD AND APPARATUS FOR DETERMINING ERROR LOCATION
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Patent #:
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|
Issue Dt:
|
08/08/1995
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Application #:
|
08082869
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Filing Dt:
|
06/29/1993
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Title:
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METHOD OF AND SYSTEM FOR LAYING OUT BUS CELLS ON AN INTEGRATED CIRCUIT CHIP
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Patent #:
|
|
Issue Dt:
|
01/17/1995
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Application #:
|
08082870
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Filing Dt:
|
06/29/1993
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Title:
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PARALLEL ENCODING APPARATUS AND METHOD IMPLEMENTING CYCLIC REDUNDANCY CHECK AND REED-SOLOMON CODES
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Patent #:
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Issue Dt:
|
08/29/1995
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Application #:
|
08150897
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Filing Dt:
|
11/12/1993
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Title:
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APPARATUS FOR CORRECTING ERRORS IN OPTICAL DISKS
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Patent #:
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Issue Dt:
|
06/24/1997
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Application #:
|
08192909
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Filing Dt:
|
02/07/1994
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Title:
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FINITE FIELD POLYNOMIAL PROCESSING MODULE FOR ERROR CONTROL CODING
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Patent #:
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Issue Dt:
|
08/29/1995
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Application #:
|
08225690
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Filing Dt:
|
04/11/1994
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Title:
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VERTICAL DETAIL ENHANCEMENT WITH STEPPED RETURN CORING
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Patent #:
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Issue Dt:
|
01/23/1996
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Application #:
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08316462
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Filing Dt:
|
09/30/1994
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Title:
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CMOS LEVEL SHIFTER WITH FEEDFORWARD CONTROL TO PREVENT LATCHING IN A WRONG LOGIC STATE
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Patent #:
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|
Issue Dt:
|
04/30/1996
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Application #:
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08493016
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Filing Dt:
|
06/21/1995
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Title:
|
HIERARCHICAL FLOORPLANNER FOR GATE ARRAY DESIGN LAYOUT
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|
|
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Patent #:
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|
Issue Dt:
|
03/10/1998
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Application #:
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08561756
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Filing Dt:
|
11/22/1995
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Title:
|
HIGH BIT RATE START CODE SEARCHING AND DETECTING CIRCUIT AND METHOD
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Patent #:
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Issue Dt:
|
06/16/1998
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Application #:
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08567592
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Filing Dt:
|
12/05/1995
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Title:
|
LOW POWER HIGH SPEED MPEG VIDEO VARIABLE LENGTH DECODER
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|
|
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Patent #:
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|
Issue Dt:
|
12/01/1998
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Application #:
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08612512
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Filing Dt:
|
03/07/1996
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Title:
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MPEG ENCODING AND DECODING SYSTEM FOR MULTIMEDIA APPLICATIONS
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|
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Patent #:
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Issue Dt:
|
10/21/1997
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Application #:
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08648795
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Filing Dt:
|
05/16/1996
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Title:
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SHARED DRAM I/O DATABUS FOR HIGH SPEED OPERATION
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|
|
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Patent #:
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|
Issue Dt:
|
04/21/1998
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Application #:
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08655132
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Filing Dt:
|
05/30/1996
|
|
Title:
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AUTOMATIC SOFTWARE LICENSE MANAGER
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|
|
|
|
Patent #:
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|
Issue Dt:
|
03/10/1998
|
Application #:
|
08659599
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Filing Dt:
|
06/06/1996
|
|
Title:
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BUFFER WITH DRIVE CHARACTERISTICS CONTROLLABLE BY SOFTWARE
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|
|
|
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Patent #:
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|
Issue Dt:
|
06/30/1998
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Application #:
|
08725685
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Filing Dt:
|
10/02/1996
|
|
Title:
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ADDRESS GENERATOR FOR ERROR CONTROL SYSTEM
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|
|
|
|
Patent #:
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|
Issue Dt:
|
08/11/1998
|
Application #:
|
08760007
|
Filing Dt:
|
12/03/1996
|
|
Title:
|
MICRO ROM TESTING SYSTEM USING MICRO ROM TIMING CIRCUITS FOR TESTING OPERATIONS
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|
|
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Patent #:
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|
Issue Dt:
|
08/25/1998
|
Application #:
|
08767135
|
Filing Dt:
|
12/19/1996
|
|
Title:
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HIGH-SPEED MAIN AMPLIFIER WITH REDUCED ACCESS AND OUTPUT DISABLE TIME PERIODS
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|
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Patent #:
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|
Issue Dt:
|
07/21/1998
|
Application #:
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08781388
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Filing Dt:
|
01/13/1997
|
|
Title:
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LATCHED DRAM WRITE BUS FOR QUICKLY CLEARING DRAM ARRAY WITH MINIMUM POWER USAGE
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|
|
|
|
Patent #:
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|
Issue Dt:
|
04/25/2000
|
Application #:
|
08828780
|
Filing Dt:
|
03/27/1997
|
|
Title:
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DMA CONTROLLER WITH SEMAPHORE COMMUNICATION PROTOCOL
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|
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Patent #:
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|
Issue Dt:
|
12/14/1999
|
Application #:
|
08842441
|
Filing Dt:
|
04/24/1997
|
|
Title:
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ADAPTABLE OUTPUT PHASE DELAY COMPENSATION CIRCUIT AND METHOD THEREOF
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|
|
|
|
Patent #:
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|
Issue Dt:
|
11/17/1998
|
Application #:
|
08845840
|
Filing Dt:
|
04/28/1997
|
|
Title:
|
THREE-TRANSISTOR STATIC STORAGE CELL
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/03/1999
|
Application #:
|
08932384
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Filing Dt:
|
09/17/1997
|
|
Title:
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MAIN AMPLIFIER WITH FAST OUTPUT DISABLEMENT
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/31/1999
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Application #:
|
08954628
|
Filing Dt:
|
10/20/1997
|
|
Title:
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RAM HAVING MULTIPLE PORTS SHARING COMMON MEMORY LOCATIONS
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|
|
|
|
Patent #:
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|
Issue Dt:
|
10/31/2000
|
Application #:
|
08984076
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Filing Dt:
|
12/03/1997
|
|
Title:
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GROUNDED PACKAGED SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREFOR
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|
|
|
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Patent #:
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|
Issue Dt:
|
08/03/1999
|
Application #:
|
08997509
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Filing Dt:
|
12/23/1997
|
|
Title:
|
DRIVING MEMORY BITLINES USING BOOSTED VOLTAGE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/08/2000
|
Application #:
|
08997541
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Filing Dt:
|
12/23/1997
|
|
Title:
|
VOLTAGE PUMP FOR INTEGRATED CIRCUIT AND OPERATING METHOD THEREOF
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/26/2000
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Application #:
|
09006190
|
Filing Dt:
|
01/13/1998
|
|
Title:
|
MULTI-PORT RAM HAVING FUNCTIONALLY IDENTICAL PORTS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/08/2000
|
Application #:
|
09006191
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Filing Dt:
|
01/13/1998
|
|
Title:
|
MUTI-PORT MEMORY DEVIVE HAVING MASKING REGISTERS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/05/2000
|
Application #:
|
09012460
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Filing Dt:
|
01/23/1998
|
|
Title:
|
INDEPENDENT CHIP SELECT FOR SRAM AND DRAM IN A MULTI-PORT RAM
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/28/1999
|
Application #:
|
09024559
|
Filing Dt:
|
02/17/1998
|
|
Title:
|
DUAL CLOCKING SCHEME IN A MULTI-PORT RAM
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/18/2000
|
Application #:
|
09064190
|
Filing Dt:
|
04/22/1998
|
|
Title:
|
OFFSET-COMPENSATED PEAK DETECTOR WITH OUTPUT BUFFERING
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/03/2001
|
Application #:
|
09227574
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Filing Dt:
|
01/08/1999
|
|
Title:
|
PROGRAMMABLE DYNAMIC RANGE SIGMA DELTA A/D CONVERTER
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|
|
|
|
Patent #:
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|
Issue Dt:
|
02/04/2003
|
Application #:
|
09250161
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Filing Dt:
|
02/16/1999
|
|
Title:
|
SELF-ADJUSTING CLOCK PHASE CONTROLLED ARCHITECTURE
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|
|
|
|
Patent #:
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|
Issue Dt:
|
08/06/2002
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Application #:
|
09291328
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Filing Dt:
|
04/15/1999
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|
Title:
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REDUCING BIAS CURRENT SETTLING TIME IN MAGNETO-RESISTIVE HEAD PRE-AMPLIFIERS
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|
|
|
|
Patent #:
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|
Issue Dt:
|
12/03/2002
|
Application #:
|
09587980
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Filing Dt:
|
06/06/2000
|
|
Title:
|
SYSTEM AND METHOD FOR TERMINAL SHORT DETECTION
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|
|
|
|
Patent #:
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|
Issue Dt:
|
10/30/2001
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Application #:
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09589118
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Filing Dt:
|
06/08/2000
|
|
Title:
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Method and apparatus for amplifier output biasing for improved overall temperature stability
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|
|
|
|
Patent #:
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|
Issue Dt:
|
04/30/2002
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Application #:
|
09589187
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Filing Dt:
|
06/08/2000
|
|
Title:
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METHOD AND APPARATUS FOR SWITCHING STAGES OF A MULTISTAGE AMPLIFIER QUICKLY BETWEEN OPERATIONAL MODES
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|
|
|
|
Patent #:
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|
Issue Dt:
|
09/21/2004
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Application #:
|
10075437
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Filing Dt:
|
02/14/2002
|
|
Publication #:
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|
Pub Dt:
|
08/14/2003
| | | | |
|
Title:
|
METHODS AND APPARATUS FOR DETECTING TERMINAL OPEN CIRCUITS AND SHORT CIRCUITS TO GROUND IN INDUCTIVE HEAD WRITE DRIVER CIRCUITS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/21/2004
|
Application #:
|
10142318
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Filing Dt:
|
05/09/2002
|
|
Publication #:
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|
Pub Dt:
|
11/20/2003
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR PROGRAMMING NON-VOLATILE, PROGRAMMABLE, ELECTRICALLY ERASABLE MEMORY USING A USB INTERFACE
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|
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Patent #:
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|
Issue Dt:
|
03/06/2007
|
Application #:
|
10172368
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Filing Dt:
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06/14/2002
|
|
Publication #:
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|
Pub Dt:
|
12/18/2003
| | | | |
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Title:
|
DIFFERENTIAL MAGNETO-RESISTIVE HEAD PRE-AMPLIFIERS FOR SINGLE POLARITY POWER SUPPLY APPLICATIONS
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