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Patent Assignment Details

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Reel/Frame:	021965/0746			Pages:	4
		Recorded:	12/12/2008
Attorney Dkt #:	F179-40.6*1
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 14

Patent #:	5386150	Issue Dt:	01/31/1995	Application #:	07795103	Filing Dt:	11/20/1991
Title:	TRACKING PULSE GENERATOR AND RAM WITH TRACKING PRECHARGE PULSE GENERATOR

Patent #:	5319592	Issue Dt:	06/07/1994	Application #:	07981797	Filing Dt:	11/25/1992
Title:	FUSE-PROGRAMMING CIRCUIT

Patent #:	5669013	Issue Dt:	09/16/1997	Application #:	08310683	Filing Dt:	09/22/1994
Title:	SYSTEM FOR TRANSFERRING M ELEMENTS X TIMES AND TRANSFERRING N ELEMENTS ONE TIME FOR AN ARRAY THAT IS X*M+N LONG RESPONSIVE TO VECTOR TYPE INSTRUCTIONS

Patent #:	5491793	Issue Dt:	02/13/1996	Application #:	08321576	Filing Dt:	10/11/1994
Title:	DEBUG SUPPORT IN A PROCESSOR CHIP

Patent #:	5617347	Issue Dt:	04/01/1997	Application #:	08406305	Filing Dt:	03/17/1995
Title:	CACHE MEMORY SYSTEM AND METHOD THEREOF FOR STORING A STAGED MEMORY ITEM AND A CACHE TAG WITHIN A SINGLE CACHE ARRAY STRUCTURE

Patent #:	5590374	Issue Dt:	12/31/1996	Application #:	08594374	Filing Dt:	01/30/1996
Title:	METHOD AND APPARATUS FOR EMPLOYING A DUMMY READ COMMAND TO AUTOMATICALLY ASSIGN A UNIQUE MEMORY ADDRESS TO AN INTERFACE CARD

Patent #:	5887160	Issue Dt:	03/23/1999	Application #:	08767953	Filing Dt:	12/17/1996
Title:	METHOD AND APPARATUS FOR COMMUNICATING INTEGER AND FLOATING POINT DATA OVER A SHARED DATA PATH IN A SINGLE INSTRUCTION PIPELINE PROCESSOR

Patent #:	6246609	Issue Dt:	06/12/2001	Application #:	09365071	Filing Dt:	07/30/1999
Title:	DECODER CIRCUIT

Patent #:	6104667	Issue Dt:	08/15/2000	Application #:	09365075	Filing Dt:	07/30/1999
Title:	CLOCK CONTROL CIRCUIT FOR GENERATING AN INTERNAL CLOCK SIGNAL WITH ONE OR MORE EXTERNAL CLOCK CYCLES BEING BLOCKED OUT AND A SYNCHRONOUS FLASH MEMORY DEVICE USING THE SAME

Patent #:	6208564	Issue Dt:	03/27/2001	Application #:	09429987	Filing Dt:	10/29/1999
Title:	HIGH VOLTAGE COMPARATOR

Patent #:	6240044	Issue Dt:	05/29/2001	Application #:	09467649	Filing Dt:	12/20/1999
Title:	HIGH SPEED ADDRESS SEQUENCER

Patent #:	6205084	Issue Dt:	03/20/2001	Application #:	09467758	Filing Dt:	12/20/1999
Title:	BURST MODE FLASH MEMORY

Patent #:	6304486	Issue Dt:	10/16/2001	Application #:	09468422	Filing Dt:	12/20/1999
Title:	SENSING TIME CONTROL DEVICE AND METHOD

Patent #:	6634008	Issue Dt:	10/14/2003	Application #:	09478978	Filing Dt:	01/06/2000
Title:	METHODOLOGY SERVER-BASED INTEGRATED CIRCUIT DESIGN

Assignor

Exec Dt:

11/04/2008

Assignee

7-1 NISHI-SHINJUKU 2-CHOME, SHINJUKU-KU

TOKYO, JAPAN 163-0722

Correspondence name and address
	JOSEPHINE E. CHANG
	P.O. BOX 7068
	PASADENA, CA 91109-7068

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