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Patent Assignment Details
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Reel/Frame:022342/0669   Pages: 4
Recorded: 03/04/2009
Attorney Dkt #:2000.163100
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 1
1
Patent #:
Issue Dt:
10/18/2011
Application #:
12397574
Filing Dt:
03/04/2009
Publication #:
Pub Dt:
11/05/2009
Title:
METHOD FOR REDUCING DEFECTS OF GATE OF CMOS DEVICES DURING CLEANING PROCESSES BY MODIFYING A PARASITIC PN JUNCTION
Assignors
1
Exec Dt:
10/28/2008
2
Exec Dt:
10/28/2008
3
Exec Dt:
09/18/2008
4
Exec Dt:
10/28/2008
Assignee
1
5204 EAST BEN WHITE BOULEVARD
AUSTIN, TEXAS 78741
Correspondence name and address
J. MIKE AMERSON
10333 RICHMOND, SUITE 1100
HOUSTON, TX 77042

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