|
Total properties:
22
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/23/2000
|
Application #:
|
08996095
|
Filing Dt:
|
12/22/1997
|
|
Title:
|
DELAYED LOCKED LOOP IMPLEMENTATION IN A SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/06/2001
|
Application #:
|
09761274
|
Filing Dt:
|
01/16/2001
|
|
Publication #:
|
|
Pub Dt:
|
05/24/2001
| | | | |
|
Title:
|
Delayed locked loop implementation in a synchronous dynamic random access memory
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/2003
|
Application #:
|
09985972
|
Filing Dt:
|
11/07/2001
|
|
Publication #:
|
|
Pub Dt:
|
03/07/2002
| | | | |
|
Title:
|
DUAL CONTROL ANALOG DELAY ELEMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/16/2002
|
Application #:
|
10022932
|
Filing Dt:
|
12/18/2001
|
|
Publication #:
|
|
Pub Dt:
|
06/06/2002
| | | | |
|
Title:
|
MULTI-STAGE LOOKUP FOR TRANSLATING BETWEEN SIGNALS OF DIFFERENT BIT LENGTHS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/16/2003
|
Application #:
|
10176704
|
Filing Dt:
|
06/20/2002
|
|
Publication #:
|
|
Pub Dt:
|
11/28/2002
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR SELECTING AN ENCRYPTION INTEGRATED CIRCUIT OPERATING MODE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/02/2003
|
Application #:
|
10279217
|
Filing Dt:
|
10/23/2002
|
|
Publication #:
|
|
Pub Dt:
|
05/15/2003
| | | | |
|
Title:
|
DELAYED LOCKED LOOP IMPLEMENTATION IN A SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/19/2003
|
Application #:
|
10290287
|
Filing Dt:
|
11/08/2002
|
|
Publication #:
|
|
Pub Dt:
|
04/17/2003
| | | | |
|
Title:
|
BITLINE PRECHARGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/28/2007
|
Application #:
|
10409141
|
Filing Dt:
|
04/09/2003
|
|
Publication #:
|
|
Pub Dt:
|
12/18/2003
| | | | |
|
Title:
|
DUAL CONTROL ANALOG DELAY ELEMENT AND RELATED DELAY METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/31/2006
|
Application #:
|
10645330
|
Filing Dt:
|
08/21/2003
|
|
Publication #:
|
|
Pub Dt:
|
07/08/2004
| | | | |
|
Title:
|
Delay locked loop implementation in a synchronous dynamic random access memory
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/12/2005
|
Application #:
|
10788003
|
Filing Dt:
|
02/27/2004
|
|
Publication #:
|
|
Pub Dt:
|
02/10/2005
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR ADAPTIVE DATA COMPRESSION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/01/2008
|
Application #:
|
10880432
|
Filing Dt:
|
06/29/2004
|
|
Publication #:
|
|
Pub Dt:
|
02/10/2005
| | | | |
|
Title:
|
LINK AGGREGATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/21/2006
|
Application #:
|
10912768
|
Filing Dt:
|
08/05/2004
|
|
Publication #:
|
|
Pub Dt:
|
03/31/2005
| | | | |
|
Title:
|
CONTENT ADDRESSABLE MEMORY ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/06/2009
|
Application #:
|
11195257
|
Filing Dt:
|
08/01/2005
|
|
Publication #:
|
|
Pub Dt:
|
12/01/2005
| | | | |
|
Title:
|
DELAY LOCKED LOOP IMPLEMENTATION IN A SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/17/2006
|
Application #:
|
11263144
|
Filing Dt:
|
10/31/2005
|
|
Publication #:
|
|
Pub Dt:
|
03/30/2006
| | | | |
|
Title:
|
SORTING METHOD AND APPARATUS USING A CAM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/29/2009
|
Application #:
|
11305433
|
Filing Dt:
|
12/14/2005
|
|
Publication #:
|
|
Pub Dt:
|
05/18/2006
| | | | |
|
Title:
|
SYNCHRONIZATION CIRCUIT AND METHOD WITH TRANSPARENT LATCHES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/22/2008
|
Application #:
|
11323814
|
Filing Dt:
|
12/29/2005
|
|
Publication #:
|
|
Pub Dt:
|
11/16/2006
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR REDUCING POOL STARVATION IN A SHARED MEMORY SWITCH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/11/2008
|
Application #:
|
11367589
|
Filing Dt:
|
03/06/2006
|
|
Publication #:
|
|
Pub Dt:
|
07/06/2006
| | | | |
|
Title:
|
HIGH SPEED DRAM ARCHITECTURE WITH UNIFORM ACCESS LATENCY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/25/2008
|
Application #:
|
11495212
|
Filing Dt:
|
07/28/2006
|
|
Publication #:
|
|
Pub Dt:
|
11/23/2006
| | | | |
|
Title:
|
FREQUENCY-DOUBLING DELAY LOCKED LOOP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/05/2008
|
Application #:
|
11636876
|
Filing Dt:
|
12/11/2006
|
|
Publication #:
|
|
Pub Dt:
|
04/12/2007
| | | | |
|
Title:
|
CHARGE PUMP FOR PLL/DLL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/03/2008
|
Application #:
|
11774881
|
Filing Dt:
|
07/09/2007
|
|
Publication #:
|
|
Pub Dt:
|
11/08/2007
| | | | |
|
Title:
|
MATCHLINE SENSE CIRCUIT AND METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/28/2010
|
Application #:
|
11804381
|
Filing Dt:
|
05/18/2007
|
|
Publication #:
|
|
Pub Dt:
|
09/27/2007
| | | | |
|
Title:
|
PORT PACKET QUEUING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/22/2011
|
Application #:
|
11833559
|
Filing Dt:
|
08/03/2007
|
|
Publication #:
|
|
Pub Dt:
|
02/14/2008
| | | | |
|
Title:
|
DUAL CONTROL ANALOG DELAY ELEMENT
|
|
