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Patent #:
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Issue Dt:
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03/21/1989
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Application #:
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06715141
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Filing Dt:
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03/22/1985
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Title:
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PROGRAMMABLE LOGIC ARRAY USING EMITTER-COUPLED LOGIC
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Patent #:
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Issue Dt:
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07/11/1989
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Application #:
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06908559
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Filing Dt:
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09/18/1986
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Title:
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FIFO MEMORY DEVICE INCLUDING CIRCUIT FOR GENERATING FLAG SIGNALS
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Patent #:
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Issue Dt:
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09/05/1989
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Application #:
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07141239
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Filing Dt:
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01/05/1988
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Title:
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ECL PROGRAMMABLE LOGIC ARRAY WITH DIRECT TESTING MEANS FOR VERIFICATION OF PROGRAMMED STATE
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Patent #:
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Issue Dt:
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08/04/1992
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Application #:
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07146020
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Filing Dt:
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01/20/1988
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Title:
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METHODS AND APPARATUS FOR CACHING INTERLOCK VARIABLES IN AN INTEGRATED CACHE MEMORY
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Patent #:
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Issue Dt:
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08/24/1993
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Application #:
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07242743
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Filing Dt:
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09/09/1988
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Title:
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BUFFER MEMORY SUBSYSTEM FOR PERIPHERAL CONTROLLERS
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Patent #:
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Issue Dt:
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05/07/1991
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Application #:
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07286200
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Filing Dt:
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12/19/1988
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Title:
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SYSTEM FOR ACCESSING THE SAME MEMORY LOCATION BY TWO DIFFERENT DEVICES
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Patent #:
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Issue Dt:
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08/07/1990
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Application #:
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07325402
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Filing Dt:
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03/17/1989
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Title:
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HIGH SPEED COMPLIMENTARY OUTPUT STAGE UTILIZING CURRENT STEERING TRANSISTORS AND A SINGLE CURRENT SOURCE
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Patent #:
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Issue Dt:
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07/31/1990
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Application #:
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07338583
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Filing Dt:
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04/17/1989
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Title:
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TEMPERATURE AND SUPPLY COMPENSATED ECL BANDGAP REFERENCE VOLTAGE GENERATOR
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Patent #:
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Issue Dt:
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03/27/1990
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Application #:
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07338584
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Filing Dt:
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04/17/1989
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Title:
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TTL BUFFER CIRCUIT WITH ACTIVE TURN-OFF
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Patent #:
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Issue Dt:
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08/28/1990
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Application #:
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07346969
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Filing Dt:
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05/03/1989
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Title:
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BICMOS DECODER
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Patent #:
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Issue Dt:
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03/20/1990
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Application #:
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07346970
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Filing Dt:
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05/03/1989
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Title:
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BICMOS READ/WRITE CONTROL AND SENSING CIRCUIT
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Patent #:
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Issue Dt:
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10/09/1990
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Application #:
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07373743
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Filing Dt:
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06/29/1989
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Title:
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CASCADING FIFO MEMORY DEVICES
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Patent #:
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Issue Dt:
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02/19/1991
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Application #:
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07413507
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Filing Dt:
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09/26/1989
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Title:
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MEMORY DEVICE WHICH CAN FUNCTION AS TWO SEPARATE MEMORIES OR A SINGLE MEMORY
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Patent #:
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Issue Dt:
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06/05/1990
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Application #:
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07415754
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Filing Dt:
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10/02/1989
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Title:
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ECL-TO-TTL TRANSLATOR CIRCUIT WITH GROUND BOUNCE PROTECTION
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Patent #:
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Issue Dt:
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05/28/1991
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Application #:
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07420985
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Filing Dt:
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10/13/1989
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Title:
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BICMOS ECL-TO-CMOS CONVERSION CIRCUIT
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Patent #:
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Issue Dt:
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11/17/1992
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Application #:
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07480426
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Filing Dt:
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02/15/1990
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Title:
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MEDIUM ATTACHMENT UNIT FOR USE WITH TWISTED PAIR LOCAL AREA NETWORK
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Patent #:
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Issue Dt:
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12/31/1991
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Application #:
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07489203
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Filing Dt:
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03/05/1990
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Title:
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INFORMATION STORAGE DEVICE WITH BATCH SELECT CAPABILITY
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Patent #:
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Issue Dt:
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11/23/1993
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Application #:
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07556046
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Filing Dt:
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07/20/1990
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Title:
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EXPANDABLE REPEATER
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Patent #:
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Issue Dt:
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02/25/1992
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Application #:
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07565384
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Filing Dt:
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08/10/1990
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Title:
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PROCESS FOR PRODUCING OPTIMUM INTRINSIC, LONG CHANNEL, AND SHORT CHANNEL MOS DEVICES IN VLSI STRUCTURES
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Patent #:
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Issue Dt:
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05/24/1994
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Application #:
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07594929
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Filing Dt:
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10/10/1990
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Title:
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SELECTABLE REPEATER PORT RECONNECTION METHOD AND APPARATUS
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Patent #:
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Issue Dt:
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11/23/1993
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Application #:
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07595061
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Filing Dt:
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10/10/1990
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Title:
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INTEGRATED MULTI-PORT REPEATER HAVING SHARED RESOURCES
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Patent #:
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Issue Dt:
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01/04/1994
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Application #:
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07595522
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Filing Dt:
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10/11/1990
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Title:
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BI-PHASE DECODER PHASE-LOCK LOOP IN CMOS
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Patent #:
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Issue Dt:
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10/26/1993
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Application #:
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07620980
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Filing Dt:
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11/30/1990
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Title:
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AUTOMATIC POLARITY DETECTION AND CORRECTION METHOD AND APPARATUS EMPLOYING LINKPULSES
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Patent #:
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Issue Dt:
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03/02/1993
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Application #:
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07760313
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Filing Dt:
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09/16/1991
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Title:
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N-CHANNEL PULL-UP TRANSISTOR WITH REDUCED BODY EFFECT
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Patent #:
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Issue Dt:
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05/23/1995
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Application #:
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07863991
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Filing Dt:
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04/06/1992
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Title:
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AUTOMATIC POLARITY DETECTION AND CORRECTION METHOD AND APPARATUS EMPLOYING LINKPULSES
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Patent #:
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Issue Dt:
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09/28/1993
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Application #:
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07897736
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Filing Dt:
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06/12/1992
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Title:
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HIGH SPEED CMOS OUTPUT BUFFER CIRCUIT MINIMIZES OUTPUT SIGNAL OSCILLATION AND STEADY STATE CURRENT
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Patent #:
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Issue Dt:
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11/16/1993
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Application #:
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07898871
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Filing Dt:
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06/15/1992
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Title:
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METHOD AND APPARATUS FOR CMOS DIFFERENTIAL DRIVER HAVING A RAPID TURNOFF
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Patent #:
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Issue Dt:
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07/05/1994
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Application #:
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07899083
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Filing Dt:
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06/15/1992
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Title:
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TWISTED PAIR MEDIUM ACCESS UNIT
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Patent #:
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Issue Dt:
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08/24/1993
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Application #:
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07914053
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Filing Dt:
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07/13/1992
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Title:
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SYNCHRONOUS CIRCUIT WITH CLOCK SKEW COMPENSATING FUNCTION AND CIRCUITS UTILIZING SAME
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Patent #:
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Issue Dt:
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05/31/1994
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Application #:
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07959230
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Filing Dt:
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10/09/1992
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Title:
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METHOD FOR ACHIEVING A HIGH QUALITY THIN OXIDE USING A SACRIFICIAL OXIDE ANNEAL
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Patent #:
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Issue Dt:
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07/12/1994
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Application #:
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07976264
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Filing Dt:
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11/13/1992
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Title:
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REDUCED NOISE, LOW POWER, HIGH SPEED OUTPUT BUFFER
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Patent #:
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Issue Dt:
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08/22/1995
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Application #:
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08010930
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Filing Dt:
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01/29/1993
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Title:
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VARIABLE STRENGTH CLOCK SIGNAL DRIVER AND METHOD OF MANUFACTURING THE SAME
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Patent #:
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Issue Dt:
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09/22/1998
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Application #:
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08011068
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Filing Dt:
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01/29/1993
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Title:
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DIGITAL CLOCK WAVEFORM GENERATOR AND METHOD FOR GENERATING A CLOCK SIGNAL
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Patent #:
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Issue Dt:
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07/04/1995
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Application #:
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08102361
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Filing Dt:
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08/05/1993
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Title:
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EXPANDABLE REPEATER
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Patent #:
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Issue Dt:
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10/10/1995
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Application #:
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08105079
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Filing Dt:
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08/11/1993
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Title:
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ALL DIGITAL ON-THE-FLY TIME DELAY CALIBRATOR
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Patent #:
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Issue Dt:
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12/26/1995
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Application #:
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08109796
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Filing Dt:
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08/20/1993
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Title:
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SLEW RATE CONTROLLER FOR HIGH SPEED BUS
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Patent #:
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Issue Dt:
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05/09/1995
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Application #:
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08112610
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Filing Dt:
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08/26/1993
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Title:
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FOURTH-ORDER CASCADED SIGMA-DELTA MODULATOR
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Patent #:
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Issue Dt:
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02/04/1997
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Application #:
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08131092
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Filing Dt:
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10/01/1993
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Title:
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SYSTEM AND METHOD FOR CONTROLLING ASSERTION OF A PERIPHERAL BUS CLOCK SIGNAL THROUGH A SLAVE DEVICE
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Patent #:
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Issue Dt:
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12/20/1994
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Application #:
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08132027
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Filing Dt:
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10/05/1993
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Title:
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PLURAL PORT MEMORY SYSTEM UTILIZING A MEMORY HAVING A READ PORT AND A WRITE PORT
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Patent #:
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Issue Dt:
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08/29/1995
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Application #:
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08147062
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Filing Dt:
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11/03/1993
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Title:
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FOURTH-ORDER CASCADED SIGMA-DELTA MODULATOR
|
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Patent #:
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Issue Dt:
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05/28/1996
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Application #:
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08160057
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Filing Dt:
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12/01/1993
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|
Title:
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ADJUSTABLE THRESHOLD VOLTAGE CONVERSION CIRCUIT
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Patent #:
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Issue Dt:
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06/27/1995
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Application #:
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08165112
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Filing Dt:
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12/10/1993
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Title:
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METHOD OF MAKING A MOS DEVICE WITH DRAIN SIDE CHANNEL IMPLANT
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Patent #:
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Issue Dt:
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08/15/1995
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Application #:
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08171091
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Filing Dt:
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12/21/1993
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Title:
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FOURTH-ORDER CASCADED SIGMA-DELTA MODULATOR
|
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Patent #:
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Issue Dt:
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07/09/1996
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Application #:
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08185137
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Filing Dt:
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01/24/1994
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Title:
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APPARATUS AND METHOD FOR AUTOMATIC SENSE AND ESTABLISHMENT OF 5V AND 3.3V OPERATION
|
|
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Patent #:
|
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Issue Dt:
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09/25/2001
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Application #:
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08186050
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Filing Dt:
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01/24/1994
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Title:
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INTEGRATED SCSI AND ETHERNET CONTROLLER ON A PCI LOCAL BUS
|
|
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Patent #:
|
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Issue Dt:
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05/23/1995
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Application #:
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08212514
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Filing Dt:
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03/11/1994
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Title:
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OPTIMIZED BINARY ADDERS AND COMPARATORS FOR INPUTS HAVING DIFFERENT WIDTHS
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Patent #:
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Issue Dt:
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02/28/1995
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Application #:
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08212516
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Filing Dt:
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03/11/1994
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Title:
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OPTIMIZED BINARY ADDER AND COMPARATOR HAVING AN IMPLICIT CONSTANT FOR AN INPUT
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Patent #:
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Issue Dt:
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11/14/1995
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Application #:
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08224946
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Filing Dt:
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04/08/1994
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Title:
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AUI TO TWISTED PAIR LOOPBACK
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|
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Patent #:
|
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Issue Dt:
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07/23/1996
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Application #:
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08251070
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Filing Dt:
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05/27/1994
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Title:
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METHOD FOR ACHIEVING A HIGH QUALITY THIN OXIDE USING A SACRIFICIAL OXIDE ANNEAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
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11/12/1996
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Application #:
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08276734
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Filing Dt:
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07/18/1994
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|
Title:
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METHOD OF OPTICAL LITHOGRAPHY USING PHASE SHIFT MASKING
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|
|
|
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Patent #:
|
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Issue Dt:
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03/12/1996
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Application #:
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08280416
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Filing Dt:
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07/26/1994
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Title:
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METHOD FOR FABRICATING THIN OXIDES FOR A SEMICONDUCTOR TECHNOLOGY
|
|
|
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Patent #:
|
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Issue Dt:
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10/01/1996
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Application #:
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08296023
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Filing Dt:
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08/25/1994
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Title:
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CLOCK CONDITIONING CIRCUIT FOR MICROPROCESSOR APPLICATIONS
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Patent #:
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Issue Dt:
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10/10/1995
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Application #:
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08300273
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Filing Dt:
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09/02/1994
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Title:
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HOLDING APPARATUS, A METAL DEPOSITION SYSTEM, AND A WAFER PROCESSING METHOD WHICH PRESERVE TOPOGRAPHICAL MARKS ON A SEMICONDUCTOR WAFER
|
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|
|
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Patent #:
|
|
Issue Dt:
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08/20/1996
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Application #:
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08335994
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Filing Dt:
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11/08/1994
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Title:
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MONITOR UTILITY FOR USE IN MANUFACTURING ENVIRONMENT
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|
|
|
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Patent #:
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|
Issue Dt:
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11/05/1996
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Application #:
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08339328
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Filing Dt:
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11/14/1994
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|
Title:
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VOLTAGE-CONTROLLED DELAY ELEMENT WITH PROGRAMMABLE DELAY
|
|
|
|
|
Patent #:
|
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Issue Dt:
|
01/07/1997
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Application #:
|
08366048
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Filing Dt:
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12/29/1994
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|
Title:
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METHOD FOR FABRICATING DEVICES FOR ELECTROSTATIC DISCHARGE PROTECTION AND VOLTAGE REFERENCES, AND THE RESULTING STRUCTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/17/1996
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Application #:
|
08385219
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Filing Dt:
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02/08/1995
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Title:
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INTEGRATED MULTI-PORT REPEATER HAVING SHARED RESOURCES
|
|
|
|
|
Patent #:
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Issue Dt:
|
12/02/1997
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Application #:
|
08391911
|
Filing Dt:
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02/21/1995
|
|
Title:
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PSEUDO-AUI LINE DRIVER AND RECEIVER CELLS FOR ETHERNET APPLICATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/13/1999
|
Application #:
|
08393619
|
Filing Dt:
|
02/22/1995
|
|
Title:
|
OPTIMIZED BINARY ADDER AND COMPARATOR HAVING AN IMPLICIT CONSTANT FOR AN INPUT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/25/1997
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Application #:
|
08410217
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Filing Dt:
|
03/24/1995
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|
Title:
|
AUTO DRAM PARITY ENABLE/DISABLE MECHANISM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/26/1999
|
Application #:
|
08423912
|
Filing Dt:
|
04/18/1995
|
|
Title:
|
METHOD AND APPARATUS FOR IMPROVED VIDEO DECOMPRESSION BY SELECTIVE REDUCTION OF SPATIAL RESOLUTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/21/1998
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Application #:
|
08424736
|
Filing Dt:
|
04/18/1995
|
|
Title:
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METHOD AND APPARATUS FOR PRESTORING DEQUANTIZATION INFORMATION FOR DCT VLC DECODING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/15/1998
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Application #:
|
08424739
|
Filing Dt:
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04/18/1995
|
|
Title:
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METHOD AND APPARATUS FOR IMPROVED VIDEO DECOMPRESSION USING PREVIOUS FRAME DCT COEFFICIENTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/14/1996
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Application #:
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08434162
|
Filing Dt:
|
05/02/1995
|
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Title:
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OPTIMIZED BINARY ADDERS AND COMPARATORS FOR INPUTS HAVING DIFFERENT WIDTHS
|
|
|
|
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Patent #:
|
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Issue Dt:
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05/06/1997
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Application #:
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08434494
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Filing Dt:
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05/04/1995
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Title:
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ORGANIZATION OF AN INTEGRATED CACHE UNIT FOR FLEXIBLE USAGE IN SUPPORTING MICROPROCESSOR OPERATIONS
|
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|
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Patent #:
|
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Issue Dt:
|
10/21/1997
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Application #:
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08443206
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Filing Dt:
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05/17/1995
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Title:
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METHOD AND APPARATUS FOR IMPROVED VIDEO DECOMPRESSION BY ADAPTIVE SELECTION OF VIDEO INPUT BUFFER PARAMETERS
|
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|
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Patent #:
|
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Issue Dt:
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12/17/1996
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Application #:
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08462009
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Filing Dt:
|
06/05/1995
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Title:
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COMBINATION PREFETCH BUFFER AND INSTRUCTION CACHE
|
|
|
|
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Patent #:
|
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Issue Dt:
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06/23/1998
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Application #:
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08464305
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Filing Dt:
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06/05/1995
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Title:
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COPPER RESERVOIR FOR REDUCING ELECTROMIGRATION EFFECTS ASSOCIATED WITH A CONDUCTIVE VIA IN A SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
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Issue Dt:
|
05/12/1998
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Application #:
|
08464351
|
Filing Dt:
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06/05/1995
|
|
Title:
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APPARATUS AND METHOD FOR REDUCING READ MISS LATENCY BY PREDICTING SEQUENTIAL INSTRUCTION READ-AHEADS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/22/1997
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Application #:
|
08467043
|
Filing Dt:
|
06/06/1995
|
|
Title:
|
SLEW RATE CONTROLLER FOR HIGH SPEED BUS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/11/1997
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Application #:
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08478324
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Filing Dt:
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06/07/1995
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Title:
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DUAL DAMASCENE WITH A PROTECTIVE MASK FOR VIA ETCHING
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Patent #:
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Issue Dt:
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01/20/1998
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Application #:
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08479718
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Filing Dt:
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06/07/1995
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Title:
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SILICON OXIME FILM
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Patent #:
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Issue Dt:
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03/25/1997
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Application #:
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08479873
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Filing Dt:
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06/07/1995
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Title:
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HOLDING APPARATUS, A METAL DEPOSITION SYSTEM, AND A WAFER PROCESSING METHOD WHICH PRESERVE TOPOGRAPHICAL MARKS ON A SEMICONDUCTOR WAFER
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Patent #:
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Issue Dt:
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07/22/1997
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Application #:
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08489725
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Filing Dt:
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06/13/1995
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Title:
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LOW-VOLTAGE RAIL-TO-RAIL OPERATIONAL AMPLIFIER
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Patent #:
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Issue Dt:
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07/30/1996
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Application #:
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08511085
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Filing Dt:
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08/03/1995
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Title:
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ANALOG VOLTAGE REFERENCE GENERATOR SYSTEM
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Patent #:
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Issue Dt:
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07/16/1996
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Application #:
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08511421
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Filing Dt:
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08/04/1995
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Title:
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POWER SUPPLY DEPENDENT METHOD OF CONTROLLING A CHARGE PUMP
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Patent #:
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Issue Dt:
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05/12/1998
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Application #:
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08517477
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Filing Dt:
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08/21/1995
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Title:
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VARIABLE STRENGTH CLOCK SIGNAL DRIVER AND METHOD OF MANUFACTURING THE SAME
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Patent #:
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Issue Dt:
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06/16/1998
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Application #:
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08519262
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Filing Dt:
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08/25/1995
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Title:
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APPARATUS AND METHOD FOR PROVIDING A FLEXIBLE RAMP UP AND RAMP DOWN OF THE SECTIONS OF A RADIO IN A WIRELESS LOCAL AREA NETWORK
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Patent #:
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Issue Dt:
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05/12/1998
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Application #:
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08521749
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Filing Dt:
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08/31/1995
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Title:
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SUPERSCALAR MICROPROCESSOR EMPLOYING A WAY PREDICTION STRUCTURE
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Patent #:
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Issue Dt:
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07/29/1997
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Application #:
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08550424
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Filing Dt:
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10/30/1995
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Title:
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METHOD FOR MAKING SEMICONDUCTOR CIRCUIT INCLUDING NON-ESD TRANSISTORS WITH REDUCED DEGRADATION DUE TO AN IMPURITY IMPLANT
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Patent #:
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Issue Dt:
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04/27/1999
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Application #:
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08555263
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Filing Dt:
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11/08/1995
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Title:
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INPUT/OUTPUT SECTION OF AN INTEGRATED CIRCUIT HAVING SEPARATE POWER DOWN CAPABILITY
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Patent #:
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Issue Dt:
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01/12/1999
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Application #:
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08555264
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Filing Dt:
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11/08/1995
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Title:
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INTEGRATED CIRCUIT INCLUDING A REALTIME CLOCK, CONFIGURATION RAM, AND MEMORY CONTROLLER IN A CORE SECTION WHICH RECEIVES AN ASYNCHRONOUS PARTIAL RESET AND AN ASYNCHRONOUS MASTER RESET
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Patent #:
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Issue Dt:
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04/07/1998
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Application #:
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08558367
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Filing Dt:
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11/16/1995
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Title:
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METHOD FOR DEPOSITING VERY THIN PECVD SIO2 IN 0.5 MICRON AND 0.35 MICRON TECHNOLOGIES
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Patent #:
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Issue Dt:
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05/11/1999
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Application #:
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08561073
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Filing Dt:
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11/20/1995
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Title:
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METHOD FOR TRANSFERRING DATA BETWEEN A PAIR OF CACHES CONFIGURED TO BE ACCESSED FROM DIFFERENT STAGES OF AN INSTRUCTION PROCESSING PIPELINE
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Patent #:
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Issue Dt:
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11/25/1997
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Application #:
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08562682
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Filing Dt:
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11/27/1995
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Title:
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BUS DRIVER CIRCUIT CONFIGURED TO PARTIALLY DISCHARGE A BUS CONDUCTOR TO DECREASE LINE TO LINE COUPLING CAPACITANCE
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Patent #:
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Issue Dt:
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07/28/1998
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Application #:
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08564695
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Filing Dt:
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11/29/1995
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Title:
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ADVANCED COPPER INTERCONNECT SYSTEM THAT IS COMPATIBLE WITH EXISTING IC WIRE BONDING TECHNOLOGY
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Patent #:
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Issue Dt:
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11/18/1997
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Application #:
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08565308
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Filing Dt:
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11/30/1995
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Title:
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CONSTRUCTION THAT PREVENTS THE UNDERCUT OF INTERCONNECT LINES IN PLASMA METAL ETCH SYSTEMS
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Patent #:
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Issue Dt:
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04/08/1997
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Application #:
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08568848
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Filing Dt:
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12/07/1995
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Title:
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TWO-STAGE MEMORY REFRESH CIRCUIT
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Patent #:
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Issue Dt:
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04/06/1999
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Application #:
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08576107
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Filing Dt:
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12/21/1995
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Title:
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METHOD AND APPARATUS FOR DISPLAYING GRAYSCALE DATA ON A MONOCHROME GRAPHIC DISPLAY `
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Patent #:
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Issue Dt:
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03/17/1998
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Application #:
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08579757
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Filing Dt:
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12/28/1995
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Title:
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METHOD OF FABRICATING TOPSIDE STRUCTURE OF A SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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05/19/1998
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Application #:
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08592209
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Filing Dt:
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01/26/1996
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Title:
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OUT-OF-ORDER LOAD/STORE EXECUTION CONTROL
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Patent #:
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Issue Dt:
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06/02/1998
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Application #:
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08594211
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Filing Dt:
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01/31/1996
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Title:
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DIGITAL ARCHITECTURE FOR RECOVERING NRZ/NRZI DATA
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Patent #:
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Issue Dt:
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04/06/1999
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Application #:
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08599878
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Filing Dt:
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02/12/1996
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Title:
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GATE OXIDE VOLTAGE LIMITED LEVEL SHIFTER AND INVERTING BUFFER
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Patent #:
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Issue Dt:
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08/03/1999
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Application #:
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08602199
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Filing Dt:
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02/16/1996
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Title:
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SYSTEM FOR ACCESSING CONTROL TO A PERIPHERAL DEVICE UTILIZING A SYNCHRONIZATION PRIMITIVE WITHIN THE PERIPHERAL DEVICE
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Patent #:
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Issue Dt:
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08/26/1997
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Application #:
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08602261
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Filing Dt:
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02/15/1996
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Title:
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SYSTEM AND TECHNIQUE FOR POWER MANAGEMENT OF A UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER BY AUTOMATIC CLOCK GATING
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Patent #:
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Issue Dt:
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09/29/1998
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Application #:
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08620099
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Filing Dt:
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03/21/1996
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Title:
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SEMICONDUCTOR CIRCUIT INCLUDING NON-ESD TRANSISTORS WITH REDUCED DEGRADATION DUE TO AN IMPURITY IMPLANT
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Patent #:
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Issue Dt:
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07/06/1999
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Application #:
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08622726
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Filing Dt:
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03/26/1996
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Title:
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AN OPERAND CACHE ADDRESSED BY THE INSTRUCTION ADDRESS FOR REDUCING LATENCY OF READ INSTRUCTION
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Patent #:
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Issue Dt:
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11/20/2001
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Application #:
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08624910
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Filing Dt:
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03/27/1996
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Title:
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PROCESS TO SEPARATE THE DOPING OF POLYGATE AND SOURCE DRAIN REGIONS IN DUAL GATE FIELD EFFECT TRANSISTORS
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Patent #:
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Issue Dt:
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12/16/1997
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Application #:
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08648255
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Filing Dt:
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05/13/1996
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Title:
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OPTIMIZED BINARY ADDERS AND COMPARATORS FOR INPUTS HAVING DIFFERENT WIDTHS
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Patent #:
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Issue Dt:
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08/31/1999
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Application #:
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08649538
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Filing Dt:
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05/17/1996
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Title:
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SYSTEM AND METHOD FOR PROVIDING MICROPROCESSOR SERIALIZATION USING PROGRAMMABLE FUSES
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