Patent Assignment Details
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| Reel/Frame: | 022825/0527 | |
| Pages: | 2 |
| | Recorded: | 06/15/2009 | | |
| Attorney Dkt #: | 8073-1152 |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
1
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Patent #:
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NONE
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Issue Dt:
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Application #:
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12484431
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Filing Dt:
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06/15/2009
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Publication #:
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Pub Dt:
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12/24/2009
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Title:
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METHOD OF VERIFYING LAYOUT OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
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Assignee
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| 1753 SHIMONUMABE, NAKAHARA-KU, KAWASAKI |
| KANAGAWA, JAPAN 211-8668 |
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Correspondence name and address
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YOUNG & THOMPSON
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209 MADISON STREET
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SUITE 500
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ALEXANDRIA, VA 22314
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