|
Total properties:
72
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/26/1991
|
Application #:
|
07305449
|
Filing Dt:
|
02/01/1989
|
|
Title:
|
METHOD OF GENERATING TESTS FOR A COMBINATIONAL LOGIC CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/05/1991
|
Application #:
|
07390784
|
Filing Dt:
|
08/08/1989
|
|
Title:
|
A CIRCUIT TO ARIBITRATE MULTIPLE REQUESTS FOR MEMORY ACCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/29/1991
|
Application #:
|
07419284
|
Filing Dt:
|
10/10/1989
|
|
Title:
|
SELF-ALIGNING METAL INTERCONNECT FABRICATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/17/1992
|
Application #:
|
07494007
|
Filing Dt:
|
03/15/1990
|
|
Title:
|
NON-VOLATILE MEMORY STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/05/1992
|
Application #:
|
07494246
|
Filing Dt:
|
03/15/1990
|
|
Title:
|
METHOD AND APPARATUS FOR MARKING OR ERASING A MARKING ON A SEMICONDUCTOR CHIP PACKAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/30/1992
|
Application #:
|
07505730
|
Filing Dt:
|
04/06/1990
|
|
Title:
|
STATIC RANDOM ACCESS MEMORY WITH PMOS PASS GATES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/11/1992
|
Application #:
|
07557228
|
Filing Dt:
|
07/24/1990
|
|
Title:
|
ROUTING INDEPENDENT CIRCUIT COMPONENTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/19/1993
|
Application #:
|
07565621
|
Filing Dt:
|
08/10/1990
|
|
Title:
|
ETCHING SYSTEM HAVING SIMPLIFIED DIFFUSER ELEMENT REMOVAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/1991
|
Application #:
|
07585023
|
Filing Dt:
|
09/17/1990
|
|
Title:
|
REUSABLE PACKAGE FOR HOLDING A SEMICONDUCTOR CHIP AND METHOD FOR REUSING THE PACKAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/02/1993
|
Application #:
|
07585334
|
Filing Dt:
|
09/19/1990
|
|
Title:
|
TIGHTLY COUPLED, LOW OVERHEAD RAM BUILT-IN SELF-TEST LOGIC WITH PARTICULAR APPLICATIONS FOR EMBEDDED MEMORIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/23/1992
|
Application #:
|
07630115
|
Filing Dt:
|
12/19/1990
|
|
Title:
|
SYSTEM FOR POSITIONING A SEMICONDUCTOR CHIP PACKAGE WITH RESPECT TO A TESTING DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/27/1992
|
Application #:
|
07680203
|
Filing Dt:
|
04/04/1991
|
|
Title:
|
WATER SEALING DEVELOP RING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/08/1992
|
Application #:
|
07681803
|
Filing Dt:
|
04/05/1991
|
|
Title:
|
INTEGRATED CIRCUIT TEST SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/08/1992
|
Application #:
|
07681807
|
Filing Dt:
|
04/05/1991
|
|
Title:
|
ION BEAM CONTAMINATION SENSOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/20/1993
|
Application #:
|
07694532
|
Filing Dt:
|
05/01/1991
|
|
Title:
|
METHOD AND APPARATUS FOR CONTROLLING SIMULTANEOUS SWITCHING OUTPUT NOISE IN BOUNDRY SCAN PATHS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/16/1996
|
Application #:
|
07723109
|
Filing Dt:
|
06/28/1991
|
|
Title:
|
SYMBOLIC ROUTING GUIDANCE FOR WIRE NETWORKS IN VLSI CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/04/1993
|
Application #:
|
07747545
|
Filing Dt:
|
08/20/1991
|
|
Title:
|
OUTPUT PAD ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT FOR MOS DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/20/1993
|
Application #:
|
07748294
|
Filing Dt:
|
08/21/1991
|
|
Title:
|
ESD PROTECTION CIRCUIT AND METHOD FOR POWER-DOWN APPLICATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/03/1993
|
Application #:
|
07812194
|
Filing Dt:
|
12/20/1991
|
|
Title:
|
HIGH POWER BUFFER WITH INCREASED CURRENT STABILITY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/12/1993
|
Application #:
|
07843488
|
Filing Dt:
|
02/28/1992
|
|
Title:
|
SELF-COMPENSATING DIGITAL DELAY SEMICONDUCTOR DEVICE WITH SELECTABLE OUTPUT DELAYS AND METHOD THEREFOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/12/1993
|
Application #:
|
07854154
|
Filing Dt:
|
03/20/1992
|
|
Title:
|
DUAL EDGE-TRIGGERED DIGITAL STORAGE ELEMENT AND METHOD THEREFOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/16/1996
|
Application #:
|
07860812
|
Filing Dt:
|
03/31/1992
|
|
Title:
|
CACHE CONTROLLER AND METHOD FOR DUMPING CONTENTS OF A CACHE DIRECTORY AND CACHE DATA RANDOM ACCESS MEMORY (RAM)
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/13/1996
|
Application #:
|
08106146
|
Filing Dt:
|
08/13/1993
|
|
Title:
|
PACKAGE STRUCTURE HAVING ACCESSIBLE CHIP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/16/1996
|
Application #:
|
08214481
|
Filing Dt:
|
03/17/1994
|
|
Title:
|
VAPOR/LIQUID PHASE SEPARATOR FOR AN OPEN TANK IPA-DRYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/11/1997
|
Application #:
|
08258180
|
Filing Dt:
|
06/10/1994
|
|
Title:
|
DENSIFICATION IN AN INTERMETAL DIELECTRIC FILM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/28/1997
|
Application #:
|
08328939
|
Filing Dt:
|
10/25/1994
|
|
Title:
|
ELECTRICALLY AND THERMALLY ENHANCED PACKAGE USING A SEPARATE SILICON SUBSTRATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/1997
|
Application #:
|
08333008
|
Filing Dt:
|
11/01/1994
|
|
Title:
|
THERMOMETRIC DIGITAL-TO-ANALOG CONVERTER OCCOUYING REDUCED CHIP AREA
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/30/1996
|
Application #:
|
08357842
|
Filing Dt:
|
12/14/1994
|
|
Title:
|
METHOD OF MAKING MICROSCOPE PROBE TIPS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/09/1996
|
Application #:
|
08375741
|
Filing Dt:
|
01/20/1995
|
|
Title:
|
NOISE ISOLATED I/O BUFFER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/11/1997
|
Application #:
|
08415183
|
Filing Dt:
|
04/03/1995
|
|
Title:
|
INTEGRATED CIRCUIT WITH VARIABLE PAD PITCH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/06/1996
|
Application #:
|
08494756
|
Filing Dt:
|
06/26/1995
|
|
Title:
|
HIGH VOLTAGE TOLERANT CMOS INPUT/OUTPUT CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/28/1997
|
Application #:
|
08504157
|
Filing Dt:
|
07/19/1995
|
|
Title:
|
PATTERNED FILLED PHOTO MASK GENERATION FOR INTEGRATED CIRCUIT MANUFACTURING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/19/1997
|
Application #:
|
08536835
|
Filing Dt:
|
09/29/1995
|
|
Title:
|
MULTI-SIZE CRYPTOGRAPHIC KEY SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/27/1998
|
Application #:
|
08540714
|
Filing Dt:
|
10/11/1995
|
|
Title:
|
THERMAL MANAGEMENT DEVICE AND METHOD FOR A COMPUTER PROCESSOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/10/1997
|
Application #:
|
08542089
|
Filing Dt:
|
10/12/1995
|
|
Title:
|
PURGE APPARATUS FOR INTEGRATED CIRCUIT TEST SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/26/1997
|
Application #:
|
08553214
|
Filing Dt:
|
11/07/1995
|
|
Title:
|
TECHNIQUE FOR IMPROVING BONDING STRENGTH OF LEADFRAME TO SUBSTRATE IN SEMICONDUCTOR IC CHIP PACKAGES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/08/1997
|
Application #:
|
08574069
|
Filing Dt:
|
12/18/1995
|
|
Title:
|
WAFER EDGE SEALING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/08/1997
|
Application #:
|
08581294
|
Filing Dt:
|
12/28/1995
|
|
Title:
|
ELECTRICALLY ENHANCED POWER QUAD FLAT PACK ARRANGEMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/10/1997
|
Application #:
|
08586041
|
Filing Dt:
|
01/16/1996
|
|
Title:
|
N-WELL RESISTOR AS A BALLAST RESISTOR FOR OUTPUT MOSFET
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/29/1997
|
Application #:
|
08589751
|
Filing Dt:
|
01/22/1996
|
|
Title:
|
MULTI-LAYERED, INTEGRATED CIRCUIT PACKAGE HAVING REDUCED PARASITIC NOISE CHARACTERISTICS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/19/1998
|
Application #:
|
08619924
|
Filing Dt:
|
03/20/1996
|
|
Title:
|
METHOD FOR OPTIMIZING PERFORMANCE VERSUS POWER CONSUMPTION USING EXTERNAL/INTERNAL CLOCK FREQUENCY RATIOS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/03/1998
|
Application #:
|
08627461
|
Filing Dt:
|
04/04/1996
|
|
Title:
|
EVENT DRIVEN POWER MANAGEMENT CONTROL CIRCUIT AND METHOD THEREFOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/12/1998
|
Application #:
|
08630685
|
Filing Dt:
|
04/12/1996
|
|
Title:
|
INTEGRATED CIRCUIT TEST APPARATUS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/1998
|
Application #:
|
08705356
|
Filing Dt:
|
08/29/1996
|
|
Title:
|
SYSTEM AND METHOD FOR ALTERING THE CLOCK FREQUENCY TO A LOGIC CONTROLLER CONTROLLING A LOGIC DEVICE RUNNING AT A FIXED FREQUENCY SLOWER THAN A COMPUTER SYSTEM RUNNING THE LOGIC DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/20/2001
|
Application #:
|
08732165
|
Filing Dt:
|
10/16/1996
|
|
Title:
|
METHOD AND SYSTEM FOR VACUUM REMOVAL OF CHEMICAL MECHANICAL POLISHING BY-PRODUCTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/05/2000
|
Application #:
|
08906341
|
Filing Dt:
|
08/05/1997
|
|
Title:
|
METHODS OF ANALYZING A RADIO SIGNAL AND METHODS OF ANALYZING A PERSONAL HANDY-PHONE SYSTEM RADIO SIGNAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/18/2000
|
Application #:
|
08906531
|
Filing Dt:
|
08/05/1997
|
|
Title:
|
METHODS OF SYNCHRONIZATION, PERSONAL HANDY-PHONE SYSTEM STATIONS AND PHASE LOCK LOOPS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/23/2001
|
Application #:
|
08947650
|
Filing Dt:
|
10/09/1997
|
|
Title:
|
METHOD AND SYSTEM FOR PSEUDO DELAYED TRANSACTIONS THROUGH A BRIDGE TO GUARANTEE ACCESS TO A SHARED RESOURCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/28/2000
|
Application #:
|
08995679
|
Filing Dt:
|
12/22/1997
|
|
Title:
|
METHOD FOR PREVENTING ELECTROCHEMICAL EROSION OF INTERCONNECT STRUCTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/15/2000
|
Application #:
|
09009567
|
Filing Dt:
|
01/20/1998
|
|
Title:
|
LOW POWER UNDERVOLTAGE DETECTOR WITH POWER DOWN MODE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/18/2000
|
Application #:
|
09022847
|
Filing Dt:
|
02/12/1998
|
|
Title:
|
PIPELINED HARDWARE IMPLEMENTATION OF A HASHING ALGORITHM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/08/2001
|
Application #:
|
09035735
|
Filing Dt:
|
03/05/1998
|
|
Title:
|
PROCESS FOR FORMING METAL INTERCONNECTS WITH REDUCED OR ELIMINATED METAL RECESS IN VIAS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/31/2000
|
Application #:
|
09052796
|
Filing Dt:
|
03/31/1998
|
|
Title:
|
PSEUDO-SCAN TESTING USING HARDWARE-ACCESSIBLE IC STRUCTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/11/2000
|
Application #:
|
09069429
|
Filing Dt:
|
04/29/1998
|
|
Title:
|
ARRANGEMENT AND METHOD FOR DRAM CELL USING SHALLOW TRENCH ISOLATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/18/2000
|
Application #:
|
09079989
|
Filing Dt:
|
05/14/1998
|
|
Title:
|
CENTRALLY CONTROLLED INTERFACE SCHEME FOR PROMOTING DESIGN REUSABLE CIRCUIT BLOCKS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/01/2000
|
Application #:
|
09087764
|
Filing Dt:
|
05/29/1998
|
|
Title:
|
SEMICONDUCTOR CALIBRATION STRUCTURES AND CALIBRATION WAFERS FOR ASCERTAINING LAYER ALIGNMENT DURING PROCESSING AND CALIBRATING MULTIPLE SEMICONDUCTOR WAFER COATING SYSTEMS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/31/2000
|
Application #:
|
09124603
|
Filing Dt:
|
07/29/1998
|
|
Title:
|
METHOD FOR FORMING VIAS THROUGH POROUS DIELECTRIC MATERIAL AND DEVICES FORMED THEREBY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/27/2000
|
Application #:
|
09130423
|
Filing Dt:
|
08/06/1998
|
|
Title:
|
POLYSILICON PILLAR HEAT SINKS FOR SEMICONDUCTOR ON INSULATOR CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/06/2001
|
Application #:
|
09144680
|
Filing Dt:
|
08/31/1998
|
|
Title:
|
HDL SIMULATION INTERFACE FOR TESTING AND VERIFYING AN ASIC MODEL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/04/2002
|
Application #:
|
09199203
|
Filing Dt:
|
11/24/1998
|
|
Title:
|
PROCESS TO CONTROL POLY SILICON PROFILES IN A DUAL DOPED POLY SILICON PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/05/2000
|
Application #:
|
09259744
|
Filing Dt:
|
02/27/1999
|
|
Title:
|
ELECTROMIGRATION BONDING PROCESS AND SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/27/2001
|
Application #:
|
09298629
|
Filing Dt:
|
04/23/1999
|
|
Title:
|
METHOD AND APPARATUS FOR IMPROVED COPPER PLATING UNIFORMITY ON A SEMICONDUCTOR WAFER USING OPTIMIZED ELECTRICAL CURRENTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/13/2001
|
Application #:
|
09312132
|
Filing Dt:
|
05/14/1999
|
|
Title:
|
METHOD AND ARRANGEMENT FOR GYRATION FILTERING WITH LOW POWER CONSUMPTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/28/2000
|
Application #:
|
09388034
|
Filing Dt:
|
09/01/1999
|
|
Title:
|
HIGH DIFFERENTIAL IMPEDANCE LOAD DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/12/2002
|
Application #:
|
09405043
|
Filing Dt:
|
09/27/1999
|
|
Title:
|
PROGRAMMABLE INTEGRATED CIRUIT STRUCTURES AND METHODS FOR MAKING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/20/2001
|
Application #:
|
09419465
|
Filing Dt:
|
10/15/1999
|
|
Title:
|
BUILT-IN SELF TEST FOR INTEGRATED DIGITAL-TO-ANALOG CONVERTERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/06/2001
|
Application #:
|
09422029
|
Filing Dt:
|
10/20/1999
|
|
Title:
|
METHODS OF SYNCHRONIZING A PERSONAL HANDY-PHONE SYSTEM STATION AND PHASE LOCK LOOPS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/10/2003
|
Application #:
|
09435133
|
Filing Dt:
|
11/04/1999
|
|
Title:
|
PREDICTIVE MECHANISM FOR ASB SLAVE RESPONSES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/21/2000
|
Application #:
|
09465151
|
Filing Dt:
|
12/16/1999
|
|
Title:
|
TRENCH-DIFFUSION CORNER ROUNDING IN A SHALLOW -TRENCH (STI) PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/17/2001
|
Application #:
|
09472384
|
Filing Dt:
|
12/23/1999
|
|
Title:
|
PAD METALLIZATION OVER ACTIVE CIRCUITRY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/23/2001
|
Application #:
|
09487008
|
Filing Dt:
|
01/19/2000
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Title:
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ARRANGEMENT FOR DRAM CELL USING SHALLOW TRENCH ISOLATION
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Patent #:
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Issue Dt:
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06/25/2002
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Application #:
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09560939
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Filing Dt:
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04/28/2000
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Title:
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SEMICONDUCTOR DEVICE WITH ANTI-REFLECTIVE STRUCTURE AND METHODS OF MANUFACTURE
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|
