|
Total properties:
23
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/07/1992
|
Application #:
|
07301607
|
Filing Dt:
|
01/24/1989
|
|
Title:
|
METHOD AND APPARATUS FOR AUTOMATIC MEMORY CONFIGURATION BY A COMPUTER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/10/1991
|
Application #:
|
07386340
|
Filing Dt:
|
07/27/1989
|
|
Title:
|
METHOD AND APPARATUS FOR ERROR DETECTION AND LOCALIZATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/20/1992
|
Application #:
|
07426489
|
Filing Dt:
|
10/23/1989
|
|
Title:
|
HIGH SPEED DUAL PORT RAM PROVIDING TO THE CPU ACCESS VIA A SELECTED PORT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/12/1993
|
Application #:
|
07435880
|
Filing Dt:
|
11/13/1989
|
|
Title:
|
METHOD AND APPARATUS FOR PIPELINING CACHE ACCESSES USING ANTICIPATORY INTIATION OF CACHE READ
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/12/1993
|
Application #:
|
07647100
|
Filing Dt:
|
01/29/1991
|
|
Title:
|
DIRECT MEMORY ACESS (DMA) REQUEST CONTROLLING ARRANGEMENT INCLUDING SAMPLE AND HOLD CIRCUITS CAPABLE OF HANDLING IMMEDIATELY SUCCESSIVE DMA REQUESTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/08/1992
|
Application #:
|
07685157
|
Filing Dt:
|
04/12/1991
|
|
Title:
|
METHOD OF VARYING THE AMOUNT OF DATA PREFETCHED TO A CACHE MEMORY IN DEPENDENCE ON THE HISTORY OF DATA REQUESTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/29/1993
|
Application #:
|
07924391
|
Filing Dt:
|
08/03/1992
|
|
Title:
|
COMPUTER SYSTEM WHICH USES A LEAST-RECENTLY-USED ALGORITHM FOR MANIPULATING DATATAGS WHEN PERFORMING CACHE REPLACEMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/22/1994
|
Application #:
|
08017972
|
Filing Dt:
|
02/12/1993
|
|
Title:
|
PROGRAMMABLE CACHE MEMORY WHICH ASSOCIATES EACH SECTION OF MAIN MEMORY TO BE CACHED WITH A STATUS BIT WHICH ENABLES/DISABLES THE CACHING ACCESSIBILITY OF THE PARTICULAR SECTION, AND WITH THE CAPABILITY OF FUNCTIONING WITH MEMORY AREAS OF VARYING SIZE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/14/2000
|
Application #:
|
08131029
|
Filing Dt:
|
10/04/1993
|
|
Title:
|
TWO STAGE CACHE MEMORY SYSTEM AND METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2001
|
Application #:
|
08258752
|
Filing Dt:
|
06/10/1994
|
|
Title:
|
SYMMETRIC MULTIPROCESSING SYSTEM WITH UNIFIED ENVIRONMENT AND DISTRIBUTED SYSTEM FUNCTIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/25/1995
|
Application #:
|
08271640
|
Filing Dt:
|
07/07/1994
|
|
Title:
|
MEMORY CONTROLLER WHICH CAN CARRY OUT A HIGH SPEED ACCESS WHEN SUPPLIED WITH INPUT ADDRESSES WITH A TIME INTERVAL LEFT BETWEEN THE INPUT ADDRESSES HAVING THE SAME ROW ADDRESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/25/1996
|
Application #:
|
08281684
|
Filing Dt:
|
07/28/1994
|
|
Title:
|
IMAGE MEMORY CONTROL DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/12/2000
|
Application #:
|
08480047
|
Filing Dt:
|
06/06/1995
|
|
Title:
|
A MULTIPROCESSOR SYSTEM FOR ENABLING SHARED ACCESS TO A MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/28/1998
|
Application #:
|
08504957
|
Filing Dt:
|
07/20/1995
|
|
Title:
|
BUS CONTROL DEVICE FOR COMPUTER SYSTEM HAVING COMPUTER AND DMA DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/25/1997
|
Application #:
|
08508186
|
Filing Dt:
|
07/27/1995
|
|
Title:
|
CACHE FLASH CONTROLLING METHOD FOR CACHE MEMORY SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/03/1999
|
Application #:
|
08552290
|
Filing Dt:
|
11/02/1995
|
|
Title:
|
REWRITABLE ROM FILE DEVICE HAVING READ/WRITE BUFFER ACCESS CONTROL VIA COPY OF REWRITABLE AREA
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/28/1999
|
Application #:
|
08554667
|
Filing Dt:
|
11/08/1995
|
|
Title:
|
PROTECTED ADDRESS RANGE IN AN ELECTRICALLY ERASABLE PROGRAMMABLE READ ONLY MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/09/1999
|
Application #:
|
08615637
|
Filing Dt:
|
03/13/1996
|
|
Title:
|
A FLASH DISASTER RECOVERY ROM AND UTILITY TO REPROGRAM MULTIPLE ROMS THE EVENT OF DATA CORRUPTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/20/2001
|
Application #:
|
08839626
|
Filing Dt:
|
04/15/1997
|
|
Title:
|
Personal Computer Interrupt Line Sharing circuit with active Interrupt Line Monitoring, And Method For Sharing A Common Interrupt Line By Active Monitoring
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/26/2000
|
Application #:
|
08855810
|
Filing Dt:
|
05/12/1997
|
|
Title:
|
SYMMETRIC MULTIPROCESSING SYSTEM WITH UNIFIED ENVIRONMENT AND DISTRIBUTED SYSTEM FUNCTIONS WHEREIN BUS OPERATIONS RELATED STORAGE SPACES ARE MAPPED INTO A SINGLE SYSTEM ADDRESS SPACE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/03/2001
|
Application #:
|
08919194
|
Filing Dt:
|
08/28/1997
|
|
Title:
|
SECOND LEVEL CACHE MEMORY SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/20/2000
|
Application #:
|
08963012
|
Filing Dt:
|
11/03/1997
|
|
Title:
|
CONTROL SYSTEM OF FIFO MEMORIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/10/2001
|
Application #:
|
09468545
|
Filing Dt:
|
12/21/1999
|
|
Title:
|
MEMORY DEVICE HAVING LINE ADDRESS COUNTER FOR MAKING NEXT LINE ACTIVE WHILE CURRENT LINE IS PROCESSED
|
|
