Patent Assignment Details
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| Reel/Frame: | 023033/0542 | |
| Pages: | 3 |
| | Recorded: | 07/30/2009 | | |
| Attorney Dkt #: | PWRLITE ASSIGNMENT |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
2
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Patent #:
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Issue Dt:
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01/17/2012
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Application #:
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12325976
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Filing Dt:
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12/01/2008
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Title:
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METHOD AND SYSTEM FOR VERIFYING POWER-OPTIMIZED ELECTRONIC DESIGNS USING EQUIVALENCY CHECKING
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Patent #:
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Issue Dt:
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06/29/2010
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Application #:
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12356797
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Filing Dt:
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01/21/2009
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Title:
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METHOD AND APPARATUS TO CLOCK-GATE A DIGITAL INTEGRATED CIRCUIT BY USE OF FEED-FORWARD QUIESCENT INPUT ANALYSIS
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Assignee
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| 2100 LOGIC DRIVE |
| SAN JOSE, CALIFORNIA 95124 |
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Correspondence name and address
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XILINX, INC.
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2100 LOGIC DRIVE
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SAN JOSE, CA 95124
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