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732
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Patent #:
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Issue Dt:
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09/03/1996
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Application #:
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08024819
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Filing Dt:
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03/01/1993
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Title:
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PROGRAMMABLE SEQUENCER HAVING INTERNAL COMPONENTS WHICH ARE MICROPROCESSOR READ/WRITE INTERFACABLE
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Patent #:
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Issue Dt:
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05/12/1998
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Application #:
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08285520
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Filing Dt:
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08/04/1994
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Title:
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SYSTEM FOR REDUCING DELAY FOR EXECUTION SUBSEQUENT TO CORRECTLY PREDICTED BRANCH INSTRUCTION USING FETCH INFORMATION STORED WITH EACH BLOCK OF INSTRUCTIONS IN CACHE
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Patent #:
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Issue Dt:
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08/17/1999
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Application #:
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08366809
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Filing Dt:
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12/30/1994
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Title:
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PROGRAMMABLE ADDRESS MAPPING MATRIX FOR SECURE NETWORKS
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Patent #:
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Issue Dt:
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03/23/1999
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Application #:
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08420737
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Filing Dt:
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04/12/1995
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Title:
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LOAD/STORE UNIT WITH MULTIPLE OLDEST OUTSTANDING INSTRUCTION POINTERS FOR COMPLETING STORE AND LOAD/STORE MISS INSTRUCTIONS
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Patent #:
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Issue Dt:
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01/12/1999
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Application #:
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08521627
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Filing Dt:
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08/31/1995
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Title:
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DATA CACHE WHICH SPECULATIVELY UPDATES A PREDICTED DATA CACHE STORAGE LOCATION WITH STORE DATA AND SUBSEQUENTLY CORRECTS MISPREDICTED UPDATES
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Patent #:
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Issue Dt:
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01/26/1999
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Application #:
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08570242
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Filing Dt:
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12/11/1995
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Title:
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SUPERSCALAR MICROPROCESSOR CONFIGURED TO PREDICT RETURN ADDRESSES FROM A RETURN STACK STORAGE
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Patent #:
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Issue Dt:
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05/16/2000
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Application #:
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08594209
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Filing Dt:
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01/31/1996
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Title:
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TRENCH ISOLATION STRUCTURES WITH OXIDIZED SILICON REGIONS AND METHOD FOR MAKING THE SAME
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Patent #:
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Issue Dt:
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08/03/1999
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Application #:
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08623022
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Filing Dt:
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03/28/1996
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Title:
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METHOD AND APPARATUS FOR SERIALIZING MICROPROCESSOR IDENTIFICATION NUMBERS
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Patent #:
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Issue Dt:
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08/10/1999
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Application #:
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08639758
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Filing Dt:
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04/29/1996
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Title:
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REDUCED BIRD'S BEAK FIELD OXIDATION PROCESS USING NITROGEN IMPLANTED INTO ACTIVE REGION
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Patent #:
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Issue Dt:
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08/22/2000
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Application #:
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08649247
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Filing Dt:
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05/17/1996
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Title:
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DEPENDENCY TABLE FOR REDUCING DEPENDENCY CHECKING HARDWARE
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Patent #:
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Issue Dt:
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08/31/1999
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Application #:
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08649809
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Filing Dt:
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05/17/1996
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Title:
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A MICROPROCESSOR CONFIGURED TO EXECUTE MULTIPLE THREADS INCLUDING INTERRUPT SERVICE ROUTINES
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Patent #:
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Issue Dt:
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07/06/1999
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Application #:
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08649984
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Filing Dt:
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05/16/1996
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Title:
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INSTRUCTION DECODER INCLUDING TWO-WAY EMULATION CODE BRANCHING
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Patent #:
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Issue Dt:
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04/23/2002
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Application #:
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08655242
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Filing Dt:
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06/05/1996
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Title:
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DIELECTRIC HAVING AN AIR GAP FORMED BETWEEN CLOSELY SPACED INTERCONNECT LINES
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Patent #:
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Issue Dt:
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06/22/1999
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Application #:
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08681105
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Filing Dt:
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07/22/1996
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Title:
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CACHE SYSTEM AND METHOD USING TAGGED CACHE LINES FOR MATCHING CACHE STRATEGY TO I/O APPLICATION
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Patent #:
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Issue Dt:
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02/16/1999
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Application #:
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08690382
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Filing Dt:
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07/26/1996
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Title:
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APPARATUS FOR ALIGNING INSTRUCTIONS USING PREDECODED SHIFT AMOUNTS EACH SHIFT AMOUNT IDENTIFYING A PATTICULAR INSTRUCTION
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Patent #:
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Issue Dt:
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05/04/1999
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Application #:
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08690384
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Filing Dt:
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07/26/1996
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Title:
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A SUPERSCALAR MICPROCESSOR HAVING SYMMETRICAL FIXED ISSUE POSITIONS EACH CONFIGURED TO EXECUTE A PARTICULAR SUBSET OF INSTRUCTIONS
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Patent #:
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Issue Dt:
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03/02/1999
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Application #:
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08690385
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Filing Dt:
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07/26/1996
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Title:
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REORDER BUFFER CONFIGURED TO ALLOCATE STORGE CAPABLE OF STORING RESULTS CORRESPONDING TO A MAXIMUM NUMBER OF CONCURRENTLY RECEIVABLE INSTRUCTIONS REGARDLESS OF A NUMBER OF INSTRUCTIONS RECEIVED
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Patent #:
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Issue Dt:
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01/18/2000
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Application #:
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08698185
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Filing Dt:
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08/15/1996
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Title:
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METHOD AND SYSTEM FOR INCREASING NETWORK INFORMATION CARRIED IN A DATA PACKET VIA PACKET TAGGING
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Patent #:
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Issue Dt:
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11/09/1999
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Application #:
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08711880
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Filing Dt:
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09/12/1996
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Title:
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SUPERSCALAR MICROPROCESSOR EMPLOYING A FUTURE FILE FOR STORING RESULTS INTO MULTIPORTION REGISTERS
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Patent #:
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Issue Dt:
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12/28/1999
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Application #:
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08726113
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Filing Dt:
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10/04/1996
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Title:
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ULTRA SHALLOW JUNCTION FORMATION USING AMORPHOUS SILICON LAYER
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Patent #:
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Issue Dt:
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10/06/1998
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Application #:
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08731956
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Filing Dt:
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10/23/1996
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Title:
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ARCHITECTURE FOR A UNIVERSAL SERIAL BUS-BASED PC SPEAKER CONTROLLER
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Patent #:
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Issue Dt:
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09/19/2000
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Application #:
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08735683
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Filing Dt:
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10/23/1996
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Title:
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BUS BRIDGE WITH UNIFIED SERIAL BUS CONTROLLER HAVING POWER MANAGEMENT CAPABILITIES
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Patent #:
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Issue Dt:
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09/01/1998
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Application #:
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08739593
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Filing Dt:
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10/30/1996
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Title:
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METHOD OF FORMING TRENCH TRANSISTOR WITH METAL SPACERS
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Patent #:
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Issue Dt:
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08/08/2000
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Application #:
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08739595
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Filing Dt:
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10/30/1996
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Title:
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METHOD OF FORMING A TRENCH TRANSISTOR WITH INSULATIVE SPACERS
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Patent #:
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Issue Dt:
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04/10/2001
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Application #:
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08740017
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Filing Dt:
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10/23/1996
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Title:
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NOISE ELIMINATION IN A USB CODEC
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Patent #:
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Issue Dt:
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12/07/1999
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Application #:
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08745475
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Filing Dt:
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11/12/1996
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Title:
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SILICIDATION AND DEEP SOURCE-DRAIN FORMATION PRIOR TO SOURCE-DRAIN EXTENSION FORMATION
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Patent #:
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Issue Dt:
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06/15/1999
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Application #:
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08748815
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Filing Dt:
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11/14/1996
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Title:
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ALTERNATIVE PROCESS FOR BPTEOS/BPSG LAYER FORMATION
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Patent #:
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Issue Dt:
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10/19/1999
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Application #:
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08760723
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Filing Dt:
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12/05/1996
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Title:
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SEMICONDUCTOR DEVICE HAVING A THIN GATE OXIDE AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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04/25/2000
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Application #:
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08761332
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Filing Dt:
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12/10/1996
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Title:
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TRANSISTOR AND PROCESS OF MAKING A TRANSISTOR HAVING AN IMPROVED LDD MASKING MATERIAL
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Patent #:
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Issue Dt:
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08/11/1998
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Application #:
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08781443
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Filing Dt:
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01/10/1997
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Title:
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GRADED MOS TRANSISTOR JUNCTION FORMED BY ALIGNING A SEQUENCE OF IMPLANTS TO A SELECTIVELY REMOVABLE POLYSILICON SIDEWALL SPACE AND OXIDE THERMALLY GROWN THEREON
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Patent #:
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Issue Dt:
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11/17/1998
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Application #:
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08781461
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Filing Dt:
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01/10/1997
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Title:
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CMOS INTEGRATED CIRCUIT FORMED BY USING REMOVABLE SPACERS TO PRODUCE ASYMMETRICAL NMOS JUNCTIONS BEFORE ASYMMETRICAL PMOS JUNCTIONS FOR OPTIMIZING THERMAL DIFFUSIVITY OF DOPANTS IMPLANTED THEREIN
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Patent #:
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Issue Dt:
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02/01/2000
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Application #:
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08785909
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Filing Dt:
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01/21/1997
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Title:
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METHOD AND SYSTEM FOR USING N2 PLASMA TREATMENT TO ELIMINATE THE OUTGASSING DEFECTS AT THE INTERFACE OF A STOP LAYER AND AN OXIDE LAYER
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Patent #:
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Issue Dt:
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06/15/1999
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Application #:
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08786004
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Filing Dt:
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01/21/1997
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Title:
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METHOD FOR FABRICATING COOPER-ALUMINUM METALLIZATION
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Patent #:
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Issue Dt:
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07/10/2001
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Application #:
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08813620
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Filing Dt:
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03/07/1997
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Title:
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MICROCONTROLLER HAVING DEDICATED HARDWARE FOR MEMORY ADDRESS SPACE EXPANSION SUPPORTING BOTH STATIC AND DYNAMIC MEMORY DEVICES
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Patent #:
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Issue Dt:
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12/04/2001
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Application #:
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08813728
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Filing Dt:
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03/07/1997
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Title:
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OVERLAPPING PERIPHERAL CHIP SELECT SPACE WITH DRAM ON A MICROCONTROLLER WITH AN INTEGRATED DRAM CONTROLLER
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Patent #:
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Issue Dt:
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02/13/2001
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Application #:
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08820965
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Filing Dt:
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03/19/1997
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Title:
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MECHANISM FOR STORING SYSTEM LEVEL ATTRIBUTES IN A TRANSLATION LOOKASIDE BUFFER
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Patent #:
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Issue Dt:
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05/09/2000
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Application #:
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08844924
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Filing Dt:
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04/21/1997
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Title:
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METHOD OF MAKING NMOS AND PMOS DEVICES WITH REDUCED MASKING STEPS
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Patent #:
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Issue Dt:
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02/02/1999
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Application #:
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08845978
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Filing Dt:
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04/30/1997
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Title:
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METHOD OF OPERATING A HIGH PERFORMANCE SUPERSCALAR MICROPROCESSOR INCLUDING A COMMON REORDER BUFFER AND COMMON REGISTER FILE FOR BOTH INTEGER AND FLOATING POINT OPERATIONS
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Patent #:
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Issue Dt:
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10/26/1999
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Application #:
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08869466
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Filing Dt:
|
06/05/1997
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Title:
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HIGH QUALITY ISOLATION FOR HIGH DENSITY AND HIGH PERFORMANCE INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
|
05/01/2001
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Application #:
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08871469
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Filing Dt:
|
06/09/1997
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Title:
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NITROGEN LINER BENEATH TRANSISTOR SOURCE/DRAIN REGIONS TO RETARD DOPANT DIFFUSION
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Patent #:
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Issue Dt:
|
12/05/2000
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Application #:
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08878787
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Filing Dt:
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06/19/1997
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Title:
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AUTOMATED MATERIAL HANDLING SYSTEM FOR A MANUFACTURING FACILITY DIVIDED INTO SEPARATE FABRICATION AREAS
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Patent #:
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Issue Dt:
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10/16/2001
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Application #:
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08882604
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Filing Dt:
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06/25/1997
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Title:
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INFORMATION PACKET RECEPTION INDICATOR FOR REDUCING THE UTILIZATION OF A HOST SYSTEM PROCESSOR UNIT
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Patent #:
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Issue Dt:
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10/24/2000
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Application #:
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08884434
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Filing Dt:
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06/27/1997
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Title:
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CACHE INCLUDING A PREFETCH WAY FOR STORING PREFETCH CACHE LINES AND CONFIGURED TO MOVE A PREFETCHED CACHE LINE TO A NON-PREFETCH WAY UPON ACCESS TO THE PREFETCHED CACHE LINE
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Patent #:
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Issue Dt:
|
12/12/2000
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Application #:
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08884435
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Filing Dt:
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06/27/1997
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Title:
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FULLY ASSOCIATE CACHE EMPLOYING LRU GROUPS FOR CACHE REPLACEMENT AND MECHANISM FOR SELECTING AN LRU GROUP
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Patent #:
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|
Issue Dt:
|
10/31/2000
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Application #:
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08893744
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Filing Dt:
|
07/11/1997
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Title:
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METHOD AND APPARATUS FOR UPPER LEVEL SUBSTRATE ISOLATION INTEGRATED WITH BULK SILICON
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Patent #:
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Issue Dt:
|
01/01/2002
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Application #:
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08919101
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Filing Dt:
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08/28/1997
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Title:
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APPARATUS AND METHOD FOR SELECTIVELY SUPPLYING DATA PACKETS BETWEEN MEDIA DOMAINS IN A NETWORK REPEATER
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Patent #:
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Issue Dt:
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05/11/1999
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Application #:
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08920649
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Filing Dt:
|
08/15/1997
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Title:
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PLURAL OPERAND BUSES OF INTERMEDIATE WIDTHS COUPLING TO NARROWER WIDTH INTEGER AND WIDER WIDTH FLOATING POINT SUPERSCALAR PROCESSING CORE
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Patent #:
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Issue Dt:
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06/06/2000
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Application #:
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08921003
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Filing Dt:
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08/29/1997
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Title:
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ANNEALING OF SILICON OXYNITRIDE AND SILICON NITRIDE FILMS TO ELIMINATE HIGH TEMPERATURE CHARGE LOSS
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Patent #:
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Issue Dt:
|
09/05/2000
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Application #:
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08929865
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Filing Dt:
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09/15/1997
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Title:
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METHOD OF MANUFACTURING AN ISOLATION REGION IN A SEMICONDUCTOR DEVICE USING A FLOWABLE OXIDE-GENERATING MATERIAL
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Patent #:
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Issue Dt:
|
04/17/2001
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Application #:
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08936276
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Filing Dt:
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09/24/1997
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Title:
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CREATION OF AN ETCH HARDMASK BY SPIN-ON TECHNIQUE
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Patent #:
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Issue Dt:
|
11/16/1999
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Application #:
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08937069
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Filing Dt:
|
09/24/1997
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Title:
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METHOD FOR FORMING ASUMMETRICAL P-CHANNEL TRANSISTOR HAVING NITRIDED OXIDE PATTERNED TO SELECTIVELY FORM A SIDEWALL SPACER
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Patent #:
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|
Issue Dt:
|
08/15/2000
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Application #:
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08942998
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Filing Dt:
|
10/02/1997
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Title:
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MULTIPLE SPACER FORMATION/REMOVAL TECHNIQUE FOR FORMING A GRADED JUNCTION
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Patent #:
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|
Issue Dt:
|
12/26/2000
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Application #:
|
08949897
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Filing Dt:
|
10/14/1997
|
|
Title:
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TRACE CACHE FOR A MICROPROCESSOR-BASED DEVICE
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Patent #:
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|
Issue Dt:
|
04/16/2002
|
Application #:
|
08950717
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Filing Dt:
|
10/15/1997
|
|
Title:
|
METHOD FOR MAKING TRANSISTOR HAVING REDUCED SERIES RESISTANCE AND METHOD FOR PRODUCING THE SAME
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|
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Patent #:
|
|
Issue Dt:
|
02/06/2001
|
Application #:
|
08967889
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Filing Dt:
|
11/12/1997
|
|
Title:
|
METHOD OF MAKING TRENCH ISOLATION STRUCTURES WITH OXIDIZED SILICON REGIONS
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Patent #:
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NONE
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Issue Dt:
|
|
Application #:
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08978754
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Filing Dt:
|
11/26/1997
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|
Publication #:
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|
Pub Dt:
|
01/03/2002
| | | | |
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Title:
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IMPROVING FIELD LEAKAGE BY USING A THIN LAYER OF NITRIDE DEPOSITED BY CHEMICAL VAPOR DEPOSITION
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Patent #:
|
|
Issue Dt:
|
11/21/2000
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Application #:
|
08982720
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Filing Dt:
|
12/02/1997
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|
Title:
|
DATA TRANSACTION TYPING FOR IMPROVED CACHING AND PREFETCHING CHARACTERISTICS
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Patent #:
|
|
Issue Dt:
|
12/14/1999
|
Application #:
|
08984229
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Filing Dt:
|
12/03/1997
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Title:
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VIA WITH BARRIER LAYER FOR IMPEDING DIFFUSION OF CONDUCTIVE MATERIAL FROM VIA INTO INSULATOR
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Patent #:
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Issue Dt:
|
09/26/2000
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Application #:
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08984547
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Filing Dt:
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12/03/1997
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Title:
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INTEGRATED CIRCUIT CHIP PACKAGE AND METHOD OF MAKING THE SAME
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Patent #:
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Issue Dt:
|
08/21/2001
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Application #:
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08989741
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Filing Dt:
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12/12/1997
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Title:
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USE OF NITRIC OXIDE SURFACE ANNEAL TO PROVIDE REACTION BARRIER FOR DEPOSITION OF TANTALUM PENTOXIDE
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Patent #:
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Issue Dt:
|
02/01/2000
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Application #:
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08991808
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Filing Dt:
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12/16/1997
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Title:
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SILICON OXIDE INSULATOR (SOI) SEMICONDUCTOR HAVING SELECTIVELY LINKED BODY
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Patent #:
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Issue Dt:
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01/16/2001
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Application #:
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08992314
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Filing Dt:
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12/17/1997
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Title:
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COMBINED PARALLEL DEBUG AND TRACE PORT
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Patent #:
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Issue Dt:
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12/28/1999
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Application #:
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08992315
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Filing Dt:
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12/17/1997
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Title:
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TRACE SYNCHRONIZATION IN A PROCESSOR
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Patent #:
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Issue Dt:
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09/12/2000
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Application #:
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08993060
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Filing Dt:
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12/18/1997
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Title:
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OXIDE SPACERS AS SOLID SOURCES FOR GALLIUM DOPANT INTRODUCTION
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Patent #:
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Issue Dt:
|
11/23/1999
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Application #:
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08993383
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Filing Dt:
|
12/18/1997
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Title:
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SEMICONDUCTOR ARRANGEMENT WITH LIGHTLY DOPED REGIONS UNDER A GATE STRUCTURE
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Patent #:
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Issue Dt:
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04/10/2001
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Application #:
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08993415
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Filing Dt:
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12/18/1997
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Title:
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A METHOD OF FORMING A SEMICONDUCTOR DEVICE HAVING INTEGRATED ELECTRODE AND ISOLATION REGION FORMATION
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Patent #:
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Issue Dt:
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01/09/2001
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Application #:
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08993889
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Filing Dt:
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12/18/1997
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Title:
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SHALLOW TRENCH ISOLATION FORMATION WITHOUT PLANARIZATION MASK
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Patent #:
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Issue Dt:
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03/27/2001
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Application #:
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08993918
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Filing Dt:
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12/18/1997
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Title:
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RAPID THERMAL ANNEAL WITH A GASEOUS DOPANT SPECIES FOR FORMATION OF LIGHTLY DOPED REGIONS
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Patent #:
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Issue Dt:
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06/05/2001
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Application #:
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08994200
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Filing Dt:
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12/19/1997
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Title:
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PROCESS FOR BREAKING SILICIDE STRINGERS EXTENDING BETWEEN SILICIDE AREAS OF DIFFERENT ACTIVE REGIONS
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Patent #:
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Issue Dt:
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09/05/2000
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Application #:
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08999807
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Filing Dt:
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11/26/1997
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Title:
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DUCT PROCESSOR COOLING FOR PERSONAL COMPUTER
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Patent #:
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Issue Dt:
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06/19/2001
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Application #:
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09017676
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Filing Dt:
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02/03/1998
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Title:
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SELF-ENCAPSULATED COPPER METALLIZATION
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Patent #:
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Issue Dt:
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08/28/2001
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Application #:
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09036127
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Filing Dt:
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03/06/1998
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Title:
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IMPROVED DAMASCENE METAL INTERCONNECTS USING HIGHLY DIRECTIONAL DEPOSITION OF BARRIER AND/OR SEED LAYERS INCLUDING (111) FILLING METAL
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Patent #:
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Issue Dt:
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01/09/2001
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Application #:
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09048192
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Filing Dt:
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03/25/1998
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Title:
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TRANSISTOR SIDEWALL SPACERS COMPOSED OF SILICON NITRIDE CVD DEPOSITED FROM A HIGH DENSITY PLASMA SOURCE
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Patent #:
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Issue Dt:
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12/09/2003
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Application #:
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09056836
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Filing Dt:
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04/07/1998
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Title:
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TRI-LEVEL SEGMENTED CONTROL TRANSISTOR AND FABRICATION METHOD
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Patent #:
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Issue Dt:
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04/27/2004
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Application #:
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09063081
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Filing Dt:
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04/21/1998
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Title:
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METHOD OF MAKING ENHANCED TRENCH OXIDE WITH LOW TEMPERATURE NITROGEN INTEGRATION
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Patent #:
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Issue Dt:
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01/16/2001
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Application #:
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09070392
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Filing Dt:
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04/30/1998
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Title:
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VARIABLE BYTE-LENGTH INSTRUCTIONS USING STATE OF FUNCTION BIT OF SECOND BYTE OF PLURALITY OF INSTRUCTIONS BYTES AS INDICATIVE OF WHETHER FIRST BYTE IS A PREFIX BYTE
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Patent #:
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Issue Dt:
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04/17/2001
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Application #:
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09076585
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Filing Dt:
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05/12/1998
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Title:
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RTA METHODS FOR TREATING A DEEP-UV RESIST MASK PRIOR TO GATE FORMATION ETCH TO IMPROVE GATE PROFILE
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Patent #:
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Issue Dt:
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08/07/2001
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Application #:
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09076661
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Filing Dt:
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05/12/1998
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Title:
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METHODS FOR TREATING A DEEP-UV RESIST MASK PRIOR TO GATE FORMATION ETCH TO IMPROVE GATE PROFILE
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Patent #:
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Issue Dt:
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01/09/2001
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Application #:
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09090466
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Filing Dt:
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06/04/1998
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Title:
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INTEGRATED CIRCUIT HAVING TRANSISTORS THAT INCLUDE INSULATIVE PUNCHTHROUGH REGIONS AND METHOD OF FORMATION
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Patent #:
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Issue Dt:
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12/24/2002
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Application #:
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09094183
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Filing Dt:
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06/09/1998
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Title:
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"MEANS USED TO ALLOW DRIVER SOFTWARE TO SELECT MOST APPROPRIATE EXECUTION CONTEXT DYNAMICALLY"
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Patent #:
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NONE
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Issue Dt:
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Application #:
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09098718
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Filing Dt:
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06/17/1998
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Publication #:
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Pub Dt:
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05/24/2001
| | | | |
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Title:
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NITROGENATED TRENCH LINER FOR IMPROVED SHALLOW TRENCH ISOLATION
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Patent #:
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Issue Dt:
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06/12/2001
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Application #:
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09128235
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Filing Dt:
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08/03/1998
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Title:
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TRENCH AND GATE DIELECTRIC FORMATION FOR SEMICONDUCTOR DEVICES
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|
|
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Patent #:
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|
Issue Dt:
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03/11/2003
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Application #:
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09129703
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Filing Dt:
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08/05/1998
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Title:
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ADVANCED FRABRICATION TECHNIQUE TO FORM ULTRA THIN GATE DIELECTRIC USING A SACRIFICAL POLYSILICON SEED LAYER
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|
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Patent #:
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|
Issue Dt:
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01/09/2001
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Application #:
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09132282
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Filing Dt:
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08/11/1998
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Title:
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A SEMICONDUCTOR DEVICE HAVING AN INTERMETALLIC LAYER ON METAL INTERCONNECTS
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|
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Patent #:
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|
Issue Dt:
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08/13/2002
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Application #:
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09153753
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Filing Dt:
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09/15/1998
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Title:
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SEMICONDUCTOR FABRICATION EMPLOYING BARRIER ATOMS INCORPORATED AT THE EDGES OF A TRENCH ISOLATION STRUCTURE
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|
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Patent #:
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Issue Dt:
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10/01/2002
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Application #:
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09157648
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Filing Dt:
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09/21/1998
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Title:
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USING SEPARATE CACHES FOR VARIABLE AND GENERATED FIXED-LENGTH INSTRUCTIONS
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|
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Patent #:
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Issue Dt:
|
06/26/2001
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Application #:
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09157719
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Filing Dt:
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09/21/1998
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Title:
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FORCING REGULARITY INTO A CISC INSTRUCTION SET BY PADDING INSTRUCTIONS
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|
|
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Patent #:
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|
Issue Dt:
|
01/16/2001
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Application #:
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09163795
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Filing Dt:
|
09/30/1998
|
|
Title:
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AN ADVANCED ISOLATION STRUCTURE FOR HIGH DENSITY SEMICONDUCTOR DEVICES
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|
|
|
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Patent #:
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|
Issue Dt:
|
01/15/2002
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Application #:
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09165609
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Filing Dt:
|
10/02/1998
|
|
Title:
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USING PADDED INSTRUCTIONS IN A BLOCK-ORIENTED CACHE
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|
|
|
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Patent #:
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|
Issue Dt:
|
07/04/2000
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Application #:
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09173233
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Filing Dt:
|
10/15/1998
|
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Title:
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TRANSISTOR HAVING A METAL SILICIDE SELF-ALIGNED TO THE GATE
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|
|
|
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Patent #:
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|
Issue Dt:
|
04/30/2002
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Application #:
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09177043
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Filing Dt:
|
10/22/1998
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Publication #:
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Pub Dt:
|
01/10/2002
| | | | |
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Title:
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DOPANT DIFFUSION-RETARDING BARRIER REGION FORMED WITHIN POLYSILICON GATE LAYER
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Patent #:
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|
Issue Dt:
|
07/31/2001
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Application #:
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09178225
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Filing Dt:
|
10/23/1998
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Title:
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TRANSISTOR WITH AN ULTRA SHORT CHANNEL LENGTH DEFINED BY A LATERALLY DIFFUSED NITROGEN IMPLANT
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Patent #:
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Issue Dt:
|
01/30/2001
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Application #:
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09187630
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Filing Dt:
|
11/06/1998
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Title:
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DUAL AMORPHIZATION IMPLANT PROCESS FOR ULTRA-SHALLOW DRAIN AND SOURCE EXTENSIONS
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Patent #:
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|
Issue Dt:
|
10/03/2000
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Application #:
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09190768
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Filing Dt:
|
11/12/1998
|
|
Title:
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METHOD FOR REMOVING COPPER RESIDUE FROM SURFACES OF A SEMICONDUCTOR WAFER
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|
|
|
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Patent #:
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|
Issue Dt:
|
04/02/2002
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Application #:
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09190986
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Filing Dt:
|
11/12/1998
|
|
Title:
|
MANUFACTURING REFERENCE DATABASE
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Patent #:
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|
Issue Dt:
|
05/23/2000
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Application #:
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09191138
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Filing Dt:
|
11/13/1998
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Title:
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SUBTRENCH CONDUCTOR FORMED WITH LARGE TILT ANGLE IMPLANT
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Patent #:
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Issue Dt:
|
10/23/2001
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Application #:
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09204630
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Filing Dt:
|
12/02/1998
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Title:
|
ULTRA-THIN RESIST AND SION/OXIDE HARD MASK FOR METAL ETCH
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Patent #:
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|
Issue Dt:
|
03/26/2002
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Application #:
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09206550
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Filing Dt:
|
12/07/1998
|
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Title:
|
SEMICONDUCTOR TOPOGRAPHY HAVING IMPROVED ACTIVE DEVICE ISOLATION AND REDUCED DOPANT MIGRATION
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Patent #:
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|
Issue Dt:
|
10/31/2000
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Application #:
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09206951
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Filing Dt:
|
12/08/1998
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Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING WITHOUT DAMAGING HSQ LAYER AND METAL PATTERN UTILIZING MULTIPLE DIELECTRIC LAYERS
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Patent #:
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|
Issue Dt:
|
04/29/2003
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Application #:
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09225219
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Filing Dt:
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01/04/1999
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Publication #:
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Pub Dt:
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10/10/2002
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Title:
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NETWORK TRANSCEIVER FOR STEERING NETWORK DATA TO SELECTED PATHS BASED ON DETERMINED LINK SPEEDS
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