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Reel/Frame:	023220/0637			Pages:	6
		Recorded:	09/15/2009
Attorney Dkt #:	NTC-P0268-USA 49 CASES
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 49

Patent #:	5474955	Issue Dt:	12/12/1995	Application #:	08427941	Filing Dt:	04/25/1995
Title:	METHOD FOR OPTIMIZING THERMAL BUDGETS IN FABRICATING SEMICONDUCTORS

Patent #:	5646075	Issue Dt:	07/08/1997	Application #:	08559511	Filing Dt:	11/15/1995
Title:	METHOD FOR OPTIMIZING THERMAL BUDGETS IN FABRICATING SEMICONDUCTORS

Patent #:	5793224	Issue Dt:	08/11/1998	Application #:	08666617	Filing Dt:	06/18/1996
Title:	VOLTAGE GENERATOR FOR ANTIFUSE PROGRAMMING

Patent #:	5910921	Issue Dt:	06/08/1999	Application #:	08838010	Filing Dt:	04/22/1997
Title:	SELF-TEST OF A MEMORY DEVICE

Patent #:	5935263	Issue Dt:	08/10/1999	Application #:	08886195	Filing Dt:	07/01/1997
Title:	METHOD AND APPARATUS FOR MEMORY ARRAY COMPRESSED DATA TESTING

Patent #:	6154851	Issue Dt:	11/28/2000	Application #:	08906754	Filing Dt:	08/05/1997
Title:	MEMORY REPAIR

Patent #:	5896334	Issue Dt:	04/20/1999	Application #:	08911667	Filing Dt:	08/14/1997
Title:	CIRCUIT AND METHOD FOR MEMORY DEVICE WITH DEFECT CURRENT ISOLATION

Patent #:	6350704	Issue Dt:	02/26/2002	Application #:	08950319	Filing Dt:	10/14/1997
Title:	POROUS SILICON OXYCARBIDE INTEGRATED CIRCUIT INSULATOR

Patent #:	5949698	Issue Dt:	09/07/1999	Application #:	09026603	Filing Dt:	02/20/1998
Title:	TWISTED GLOBAL COLUMN DECODER

Patent #:	6162744	Issue Dt:	12/19/2000	Application #:	09033064	Filing Dt:	02/28/1998
Title:	METHOD OF FORMING HIGH-K OXYGEN-CONTAINING DIELECTRIC LAYERS INCLUDING MANUFACTURE OF CAPACITORS AND DRAM CELLS

Patent #:	6284656	Issue Dt:	09/04/2001	Application #:	09128859	Filing Dt:	08/04/1998
Title:	COPPER METALLURGY IN INTEGRATED CIRCUITS

Patent #:	6265282	Issue Dt:	07/24/2001	Application #:	09135474	Filing Dt:	08/17/1998
Title:	A PROCESS FOR MAKING AN ISOLATION STRUCTURE

Patent #:	6118728	Issue Dt:	09/12/2000	Application #:	09237362	Filing Dt:	01/26/1999
Title:	CIRCUIT AND METHOD FOR MEMORY DEVICE WITH DEFECT CURRENT ISOLATION

Patent #:	6041003	Issue Dt:	03/21/2000	Application #:	09261607	Filing Dt:	02/26/1999
Title:	CIRCUIT AND METHOD FOR MEMORY DEVICE WITH DEFECT CURRENT ISOLATION

Patent #:	6218256	Issue Dt:	04/17/2001	Application #:	09291127	Filing Dt:	04/13/1999
Title:	METHODS OF MANUFACTURING ELECTRODE AND CAPACITOR STRUCTURES FOR A SEMICONDUCTOR DEVICE

Patent #:	6535999	Issue Dt:	03/18/2003	Application #:	09352352	Filing Dt:	07/13/1999
Title:	TEST AND OBSERVE MODE FOR EMBEDDED MEMORY

Patent #:	6111774	Issue Dt:	08/29/2000	Application #:	09362076	Filing Dt:	07/27/1999
Title:	TWISTED GLOBAL COLUMN DECODER

Patent #:	6521958	Issue Dt:	02/18/2003	Application #:	09383804	Filing Dt:	08/26/1999
Title:	MOSFET TECHNOLOGY FOR PROGRAMMABLE ADDRESS DECODE AND CORRECTION

Patent #:	6399983	Issue Dt:	06/04/2002	Application #:	09389294	Filing Dt:	09/02/1999
Title:	REDUCTION OF SHORTS AMONG ELECTRICAL CELLS FORMED ON A SEMICONDUCTOR SUBSTRATE

Patent #:	6753584	Issue Dt:	06/22/2004	Application #:	09476558	Filing Dt:	01/03/2000
Title:	ANTIREFLECTIVE COATING LAYER

Patent #:	6313518	Issue Dt:	11/06/2001	Application #:	09517029	Filing Dt:	03/02/2000
Publication #:	US20010038132	Pub Dt:	11/08/2001
Title:	Porous silicon oxycarbide integrated circuit insulator

Patent #:	6154401	Issue Dt:	11/28/2000	Application #:	09528400	Filing Dt:	03/20/2000
Title:	Circuit and method for memory device with defect current isolation

Patent #:	6480408	Issue Dt:	11/12/2002	Application #:	09583439	Filing Dt:	05/31/2000
Title:	TWISTED GLOBAL COLUMN DECODER

Patent #:	6627389	Issue Dt:	09/30/2003	Application #:	09631264	Filing Dt:	08/02/2000
Title:	PHOTOLITHOGRAPHY METHOD USING AN ANTIREFLECTIVE COATING

Patent #:	6333882	Issue Dt:	12/25/2001	Application #:	09645577	Filing Dt:	08/25/2000
Title:	Equilibration/pre-charge circuit for a memory device

Patent #:	6301164	Issue Dt:	10/09/2001	Application #:	09648921	Filing Dt:	08/25/2000
Title:	Antifuse method to repair columns in a prefetched output memory architecture

Patent #:	6373290	Issue Dt:	04/16/2002	Application #:	09651630	Filing Dt:	08/30/2000
Title:	Clock-delayed pseudo-nmos domino logic

Patent #:	6574128	Issue Dt:	06/03/2003	Application #:	09651639	Filing Dt:	08/30/2000
Title:	MID ARRAY ISOLATE CIRCUIT LAYOUT

Patent #:	6346746	Issue Dt:	02/12/2002	Application #:	09654997	Filing Dt:	08/31/2000
Title:	CAPACITOR AND ELECTRODE STRUCTURES FOR A SEMICONDUCTOR DEVICE

Patent #:	6664634	Issue Dt:	12/16/2003	Application #:	09805913	Filing Dt:	03/15/2001
Publication #:	US20020131289	Pub Dt:	09/19/2002
Title:	IMPROVED METAL WIRING PATTERN FOR MEMORY DEVICES

Patent #:	6803326	Issue Dt:	10/12/2004	Application #:	09909532	Filing Dt:	07/20/2001
Publication #:	US20020048968	Pub Dt:	04/25/2002
Title:	POROUS SILICON OXYCARBIDE INTEGRATED CIRCUIT INSULATOR

Patent #:	6414364	Issue Dt:	07/02/2002	Application #:	09911580	Filing Dt:	07/24/2001
Publication #:	US20010044193	Pub Dt:	11/22/2001
Title:	ISOLATION STRUCTURE AND PROCESS THEREFOR

Patent #:	6700821	Issue Dt:	03/02/2004	Application #:	09924659	Filing Dt:	08/08/2001
Publication #:	US20020027264	Pub Dt:	03/07/2002
Title:	MOSFET TECHNOLOGY FOR PROGRAMMABLE ADDRESS DECODE AND CORRECTION

Patent #:	6614099	Issue Dt:	09/02/2003	Application #:	09946055	Filing Dt:	09/04/2001
Publication #:	US20020006725	Pub Dt:	01/17/2002
Title:	COPPER METALLURGY IN INTEGRATED CIRCUITS

Patent #:	6614085	Issue Dt:	09/02/2003	Application #:	10003522	Filing Dt:	10/31/2001
Publication #:	US20020105043	Pub Dt:	08/08/2002
Title:	ANTIREFLECTIVE COATING LAYER

Patent #:	6710428	Issue Dt:	03/23/2004	Application #:	10083051	Filing Dt:	02/26/2002
Publication #:	US20020079557	Pub Dt:	06/27/2002
Title:	POROUS SILICON OXYCARBIDE INTEGRATED CIRCUIT INSULATOR

Patent #:	6714434	Issue Dt:	03/30/2004	Application #:	10229555	Filing Dt:	08/28/2002
Publication #:	US20030012047	Pub Dt:	01/16/2003
Title:	MID ARRAY ISOLATE CIRCUIT LAYOUT

Patent #:	6936909	Issue Dt:	08/30/2005	Application #:	10230928	Filing Dt:	08/29/2002
Publication #:	US20040041167	Pub Dt:	03/04/2004
Title:	GATE DIELECTRIC ANTIFUSE CIRCUIT TO PROTECT A HIGH-VOLTAGE TRANSISTOR

Patent #:	6754131	Issue Dt:	06/22/2004	Application #:	10231389	Filing Dt:	08/29/2002
Publication #:	US20040042321	Pub Dt:	03/04/2004
Title:	WORD LINE DRIVER FOR NEGATIVE VOLTAGE

Patent #:	6888769	Issue Dt:	05/03/2005	Application #:	10231626	Filing Dt:	08/29/2002
Publication #:	US20040042304	Pub Dt:	03/04/2004
Title:	METHOD AND CIRCUIT FOR REDUCING DRAM REFRESH POWER BY REDUCING ACCESS TRANSISTOR SUB THRESHOLD LEAKAGE

Patent #:	6809986	Issue Dt:	10/26/2004	Application #:	10232953	Filing Dt:	08/29/2002
Publication #:	US20040042322	Pub Dt:	03/04/2004
Title:	SYSTEM AND METHOD FOR NEGATIVE WORD LINE DRIVER CIRCUIT

Patent #:	6728151	Issue Dt:	04/27/2004	Application #:	10233997	Filing Dt:	08/29/2002
Publication #:	US20040042305	Pub Dt:	03/04/2004
Title:	DRIVING A DRAM SENSE AMPLIFIER HAVING LOW THRESHOLD VOLTAGE PMOS TRANSISTORS

Patent #:	7254756	Issue Dt:	08/07/2007	Application #:	10696971	Filing Dt:	10/30/2003
Publication #:	US20040153599	Pub Dt:	08/05/2004
Title:	DATA COMPRESSION READ MODE FOR MEMORY TESTING

Patent #:	6909635	Issue Dt:	06/21/2005	Application #:	10763136	Filing Dt:	01/22/2004
Publication #:	US20040151029	Pub Dt:	08/05/2004
Title:	PROGRAMMABLE MEMORY CELL USING CHARGE TRAPPING IN A GATE OXIDE

Patent #:	7002863	Issue Dt:	02/21/2006	Application #:	10783976	Filing Dt:	02/20/2004
Publication #:	US20040246790	Pub Dt:	12/09/2004
Title:	DRIVING A DRAM SENSE AMPLIFIER HAVING LOW THRESHOLD VOLTAGE PMOS TRANSISTORS

Patent #:	7203124	Issue Dt:	04/10/2007	Application #:	10860881	Filing Dt:	06/03/2004
Publication #:	US20040218415	Pub Dt:	11/04/2004
Title:	SYSTEM AND METHOD FOR NEGATIVE WORD LINE DRIVER CIRCUIT

Patent #:	7038958	Issue Dt:	05/02/2006	Application #:	10926357	Filing Dt:	08/26/2004
Publication #:	US20060044901	Pub Dt:	03/02/2006
Title:	DUAL STAGE DRAM MEMORY EQUALIZATION

Patent #:	7101738	Issue Dt:	09/05/2006	Application #:	10931366	Filing Dt:	08/31/2004
Publication #:	US20050029598	Pub Dt:	02/10/2005
Title:	GATE DIELECTRIC ANTIFUSE CIRCUIT TO PROTECT A HIGH-VOLTAGE TRANSISTOR

Patent #:	7023751	Issue Dt:	04/04/2006	Application #:	11040959	Filing Dt:	01/19/2005
Publication #:	US20050141309	Pub Dt:	06/30/2005
Title:	METHOD AND CIRCUIT FOR REDUCING DRAM REFRESH POWER BY REDUCING ACCESS TRANSISTOR SUB THRESHOLD LEAKAGE

Assignor

MICRON TECHNOLOGY, INC.

Exec Dt:

06/05/2009

Assignee

NANYA TECHNOLOGY CORP.

HWA-YA TECHNOLOGY PARK 669, FUHSING 3 RD., KUEISHAN

TAO-YUAN HSIEN, TAIWAN

Correspondence name and address
	WINSTON HSU
	P.O.BOX 506
	MERRIFIELD, VA 22116

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