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Reel/Frame:023330/0760   Pages: 7
Recorded: 10/07/2009
Attorney Dkt #:INOVYS ASSIGNMENTS
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 22
1
Patent #:
Issue Dt:
07/08/2003
Application #:
09796003
Filing Dt:
02/27/2001
Title:
SYSTEMS FOR PROVIDING ZERO LATENCY, NON-MODULO LOOPING AND BRANCHING OF TEST PATTERN DATA FOR AUTOMATIC TEST EQUIPMENT
2
Patent #:
Issue Dt:
04/18/2006
Application #:
10173199
Filing Dt:
06/14/2002
Title:
SYSTEM FOR DYNAMIC RE-ALLOCATION OF TEST PATTERN DATA FOR PARALLEL AND SERIAL TEST DATA PATTERNS
3
Patent #:
Issue Dt:
04/12/2005
Application #:
10210976
Filing Dt:
08/02/2002
Title:
DYNAMICALLY RECONFIGURABLE PRECISION SIGNAL DELAY TEST SYSTEM FOR AUTOMATIC TEST EQUIPMENT
4
Patent #:
Issue Dt:
06/15/2004
Application #:
10356048
Filing Dt:
01/31/2003
Title:
PROGRAMMABLE PRECISION CURRENT CONTROLLING APPARATUS
5
Patent #:
Issue Dt:
01/04/2005
Application #:
10429099
Filing Dt:
05/01/2003
Title:
SYSTEMS FOR PROVIDING ZERO LATENCY, NON-MODULO LOOPING AND BRANCHING OF TEST PATTERN DATA FOR AUTOMATIC TEST EQUIPMENT
6
Patent #:
Issue Dt:
05/31/2005
Application #:
10613848
Filing Dt:
07/03/2003
Title:
DIGITALLY CONTROLLED MODULAR POWER SUPPLY FOR AUTOMATED TEST EQUIPMENT
7
Patent #:
Issue Dt:
05/16/2006
Application #:
10642000
Filing Dt:
08/15/2003
Title:
METHOD AND SYSTEM FOR AUTOMATICALLY DETERMINING A TESTING ORDER WHEN EXECUTING A TEST FLOW
8
Patent #:
NONE
Issue Dt:
Application #:
10741110
Filing Dt:
12/19/2003
Publication #:
Pub Dt:
09/15/2005
Title:
Method and system for delay defect location when testing digital semiconductor devices
9
Patent #:
Issue Dt:
03/14/2006
Application #:
10754968
Filing Dt:
01/09/2004
Title:
DYNAMICALLY RECONFIGURABLE PRECISION SIGNAL DELAY TEST SYSTEM FOR AUTOMATIC TEST EQUIPMENT
10
Patent #:
Issue Dt:
02/22/2005
Application #:
10859642
Filing Dt:
06/02/2004
Title:
PROGRAMMABLE PRECISION CURRENT CONTROLLING APPARATUS
11
Patent #:
Issue Dt:
09/26/2006
Application #:
10917898
Filing Dt:
08/12/2004
Title:
DYNAMICALLY RECONFIGURABLE PRECISION SIGNAL DELAY TEST SYSTEM FOR AUTOMATIC TEST EQUIPMENT
12
Patent #:
Issue Dt:
12/26/2006
Application #:
11087157
Filing Dt:
03/22/2005
Title:
DIGITALLY CONTROLLED MODULAR POWER SUPPLY FOR AUTOMATED TEST EQUIPMENT
13
Patent #:
Issue Dt:
08/23/2011
Application #:
11563612
Filing Dt:
11/27/2006
Publication #:
Pub Dt:
05/29/2008
Title:
SYSTEM AND METHOD FOR DEVICE PERFORMANCE CHARACTERIZATION IN PHYSICAL AND LOGICAL DOMAINS WITH AC SCAN TESTING
14
Patent #:
Issue Dt:
05/28/2013
Application #:
11565616
Filing Dt:
11/30/2006
Publication #:
Pub Dt:
05/01/2008
Title:
PROCESS FOR IMPROVING DESIGN LIMITED YIELD BY EFFICIENTLY CAPTURING AND STORING PRODUCTION TEST DATA FOR ANALYSIS USING CHECKSUMS, HASH VALUES, OR DIGITAL FAULT SIGNATURES
15
Patent #:
Issue Dt:
07/28/2009
Application #:
11609899
Filing Dt:
12/12/2006
Publication #:
Pub Dt:
06/12/2008
Title:
PROCESS FOR IDENTIFYING THE LOCATION OF A BREAK IN A SCAN CHAIN IN REAL TIME
16
Patent #:
Issue Dt:
01/19/2010
Application #:
11680134
Filing Dt:
02/28/2007
Publication #:
Pub Dt:
08/28/2008
Title:
APPARATUS FOR LOCATING A DEFECT IN A SCAN CHAIN WHILE TESTING DIGITAL LOGIC
17
Patent #:
Issue Dt:
12/24/2013
Application #:
11682314
Filing Dt:
03/06/2007
Publication #:
Pub Dt:
04/17/2008
Title:
PROCESS FOR IMPROVING DESIGN-LIMITED YIELD BY LOCALIZING POTENTIAL FAULTS FROM PRODUCTION TEST DATA
18
Patent #:
Issue Dt:
11/15/2011
Application #:
11850342
Filing Dt:
09/05/2007
Publication #:
Pub Dt:
02/04/2010
Title:
METHOD FOR OPERATING A SECURE SEMICONDUCTOR IP SERVER TO SUPPORT FAILURE ANALYSIS
19
Patent #:
Issue Dt:
12/14/2010
Application #:
11931847
Filing Dt:
10/31/2007
Publication #:
Pub Dt:
04/30/2009
Title:
LOCATING HOLD TIME VIOLATIONS IN SCAN CHAINS BY GENERATING PATTERNS ON ATE
20
Patent #:
Issue Dt:
01/04/2011
Application #:
11941026
Filing Dt:
11/15/2007
Publication #:
Pub Dt:
05/21/2009
Title:
DYNAMIC MASK MEMORY FOR SERIAL SCAN TESTING
21
Patent #:
Issue Dt:
08/30/2011
Application #:
12058768
Filing Dt:
03/31/2008
Publication #:
Pub Dt:
04/30/2009
Title:
METHODS FOR ANALYZING SCAN CHAINS, AND FOR DETERMINING NUMBERS OR LOCATIONS OF HOLD TIME FAULTS IN SCAN CHAINS
22
Patent #:
Issue Dt:
02/28/2012
Application #:
12074015
Filing Dt:
02/28/2008
Publication #:
Pub Dt:
09/04/2008
Title:
METHODS AND APPARATUS FOR ESTIMATING A POSITION OF A STUCK-AT DEFECT IN A SCAN CHAIN OF A DEVICE UNDER TEST
Assignor
1
Exec Dt:
10/06/2009
Assignee
1
NO. 1 YISHUN AVENUE 7
LOT 1937C, 1935X, 1975P
SINGAPORE, SINGAPORE 768923
Correspondence name and address
GREGORY W. OSTERLOTH
P.O. BOX 8749
DENVER, CO 80201

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