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Reel/Frame:023519/0078   Pages: 5
Recorded: 11/15/2009
Attorney Dkt #:INFINEON ASSIGNMENTS
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 25
1
Patent #:
Issue Dt:
05/03/1994
Application #:
07991776
Filing Dt:
12/16/1992
Title:
PROCESS FOR THE MANUFACTURE OF A HIGH DENSITY CELL ARRAY OF GAIN MEMORY CELLS
2
Patent #:
Issue Dt:
08/22/1995
Application #:
07995639
Filing Dt:
12/17/1992
Title:
DECODED-SOURCE SENSE AMPLIFIER WITH SPECIAL COLUMN SELECT DRIVER VOLTAGE
3
Patent #:
Issue Dt:
12/08/1998
Application #:
08829256
Filing Dt:
03/31/1997
Title:
VOLTAGE DETECTION CIRCUIT AND INTERNAL VOLTAGE CLAMP CIRCUIT
4
Patent #:
Issue Dt:
08/03/1999
Application #:
08856336
Filing Dt:
05/14/1997
Title:
MOSFETS WITH IMPROVED SHORT CHANNEL EFFECTS
5
Patent #:
Issue Dt:
11/09/1999
Application #:
09034517
Filing Dt:
03/04/1998
Title:
METHOD AND APPARATUS FOR EVALUATING INTERNAL FILM STRESS AT HIGH LATERAL RESOLUTION
6
Patent #:
Issue Dt:
05/06/2003
Application #:
09801413
Filing Dt:
03/08/2001
Publication #:
Pub Dt:
09/12/2002
Title:
APPARATUS AND METHOD FOR PATTERNING A SEMICONDUCTOR WAFER
7
Patent #:
Issue Dt:
03/04/2003
Application #:
09876706
Filing Dt:
06/07/2001
Publication #:
Pub Dt:
12/20/2001
Title:
INTEGRATED CIRCUIT CONFIGURATION FOR TESTING TRANSISTORS, AND A SEMICONDUCTOR WAFER HAVING SUCH A CIRCUIT CONFIGURATION
8
Patent #:
Issue Dt:
04/29/2003
Application #:
09907695
Filing Dt:
07/18/2001
Publication #:
Pub Dt:
01/31/2002
Title:
SYSTEM FOR TESTING FAST SYNCHRONOUS SEMICONDUCTOR CIRCUITS
9
Patent #:
Issue Dt:
03/16/2004
Application #:
09914749
Filing Dt:
01/14/2002
Title:
METHOD FOR IMPROVING THERMAL PROCESS STEPS
10
Patent #:
Issue Dt:
06/15/2004
Application #:
09915984
Filing Dt:
07/25/2001
Publication #:
Pub Dt:
02/21/2002
Title:
APPARATUS FOR TESTING SEMICONDUCTOR DEVICES
11
Patent #:
Issue Dt:
09/02/2003
Application #:
09947295
Filing Dt:
09/05/2001
Publication #:
Pub Dt:
07/04/2002
Title:
MEASUREMENT PROBE FOR DETECTING ELECTRICAL SIGNALS IN AN INTEGRATED SEMICONDUCTOR CIRCUIT
12
Patent #:
Issue Dt:
04/20/2004
Application #:
09992290
Filing Dt:
11/16/2001
Publication #:
Pub Dt:
06/20/2002
Title:
METHOD OF CALIBRATING A TEST SYSTEM FOR SEMICONDUCTOR COMPONENTS, AND TEST SUBSTRATE
13
Patent #:
Issue Dt:
07/13/2004
Application #:
10010504
Filing Dt:
12/05/2001
Publication #:
Pub Dt:
07/11/2002
Title:
TEST CONFIGURATION AND TEST METHOD FOR TESTING A PLURALITY OF INTEGRATED CIRCUITS IN PARALLEL
14
Patent #:
Issue Dt:
08/10/2004
Application #:
10105590
Filing Dt:
03/25/2002
Publication #:
Pub Dt:
09/26/2002
Title:
METHOD FOR RELEASABLE CONTACT-CONNECTION OF A PLURALITY OF INTEGRATED SEMICONDUCTOR MODULES ON A WAFER
15
Patent #:
Issue Dt:
08/31/2004
Application #:
10131374
Filing Dt:
04/24/2002
Publication #:
Pub Dt:
10/24/2002
Title:
CIRCUIT CONFIGURATION FOR SELECTIVELY TRANSMITTING INFORMATION ITEMS FROM A MEASURING DEVICE TO CHIPS ON A WAFER DURING CHIP FABRICATION
16
Patent #:
Issue Dt:
01/13/2004
Application #:
10134132
Filing Dt:
04/29/2002
Publication #:
Pub Dt:
10/31/2002
Title:
TEST APPARATUS FOR PARALLEL TESTING A NUMBER OF ELECTRONIC COMPONENTS AND A METHOD FOR CALIBRATING THE TEST APPARATUS
17
Patent #:
Issue Dt:
07/01/2003
Application #:
10177945
Filing Dt:
06/20/2002
Publication #:
Pub Dt:
01/16/2003
Title:
DELAY LOCKED LOOP
18
Patent #:
Issue Dt:
09/02/2003
Application #:
10186659
Filing Dt:
07/01/2002
Publication #:
Pub Dt:
01/02/2003
Title:
TESTER APPARATUS FOR ELECTRONIC COMPONENTS
19
Patent #:
Issue Dt:
05/04/2004
Application #:
10206299
Filing Dt:
07/26/2002
Publication #:
Pub Dt:
01/30/2003
Title:
INTEGRATED DYNAMIC MEMORY AND OPERATING METHOD
20
Patent #:
Issue Dt:
08/24/2004
Application #:
10208252
Filing Dt:
07/30/2002
Publication #:
Pub Dt:
02/20/2003
Title:
CIRCUIT FOR TESTING AN INTEGRATED CIRCUIT
21
Patent #:
Issue Dt:
03/09/2004
Application #:
10223899
Filing Dt:
08/20/2002
Publication #:
Pub Dt:
02/20/2003
Title:
METHOD FOR DETERMINING THE TRANSIT TIME OF ELECTRICAL SIGNALS ON PRINTED CIRCUIT BOARDS USING AUTOMATIC STANDARD TEST EQUIPMENT
22
Patent #:
Issue Dt:
02/01/2005
Application #:
10386148
Filing Dt:
03/11/2003
Publication #:
Pub Dt:
11/20/2003
Title:
TEMPERATURE-DEPENDENT REFRESH CYCLE FOR DRAM
23
Patent #:
Issue Dt:
02/08/2005
Application #:
10736356
Filing Dt:
12/15/2003
Publication #:
Pub Dt:
07/01/2004
Title:
METHOD AND PROBE CARD CONFIGURATION FOR TESTING A PLURALITY OF INTEGRATED CIRCUITS IN PARALLEL
24
Patent #:
Issue Dt:
12/06/2005
Application #:
10834416
Filing Dt:
04/29/2004
Publication #:
Pub Dt:
01/06/2005
Title:
APPARATUS FOR FLEXIBLE DEACTIVATION OF WORD LINES OF DYNAMIC MEMORY MODULES AND METHOD THEREFOR
25
Patent #:
Issue Dt:
11/29/2005
Application #:
10965513
Filing Dt:
10/14/2004
Publication #:
Pub Dt:
03/03/2005
Title:
APPARATUS FOR THE AUTOMATED TESTING, CALIBRATION AND CHARACTERIZATION OF TEST ADAPTERS
Assignor
1
Exec Dt:
09/05/2006
Assignee
1
GUSTAV-HEINEMANN-RING 212
MUNICH, GERMANY
Correspondence name and address
MOSAID TECHNOLOGIES INCORPORATED
11 HINES ROAD
SUITE 203
OTTAWA, K2K 2X1 CANADA

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