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Patent #:
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Issue Dt:
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01/26/1999
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Application #:
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08651305
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Filing Dt:
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05/23/1996
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Title:
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SEMICONDUCTOR ARRAY WITH SELF-ADJUSTED CONTACTS
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Patent #:
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Issue Dt:
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03/21/2006
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Application #:
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09756415
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Filing Dt:
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01/08/2001
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Publication #:
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Pub Dt:
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07/11/2002
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Title:
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SELF-ALIGNED COLLAR AND STRAP FORMATION FOR SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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09/24/2002
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Application #:
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09758479
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Filing Dt:
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01/11/2001
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Publication #:
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Pub Dt:
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09/12/2002
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Title:
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DELAY LOCK LOOP AND UPDATE METHOD WITH LIMITED DRIFT AND IMPROVED POWER SAVINGS
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Patent #:
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Issue Dt:
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05/25/2004
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Application #:
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09867518
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Filing Dt:
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05/31/2001
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Publication #:
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Pub Dt:
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12/05/2002
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Title:
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METHOD FOR REMOVING POLYSILANE FROM A SEMICONDUCTOR WITHOUT STRIPPING
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Patent #:
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Issue Dt:
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10/29/2002
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Application #:
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09871855
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Filing Dt:
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05/31/2001
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Title:
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DELIVERING A FINE DELAY STAGE FOR A DELAY LOCKED LOOP
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Patent #:
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Issue Dt:
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01/07/2003
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Application #:
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09875320
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Filing Dt:
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06/06/2001
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Publication #:
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Pub Dt:
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12/12/2002
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Title:
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NOTCHED GATE CONFIGURATION FOR HIGH PERFORMANCE INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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08/26/2003
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Application #:
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09888193
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Filing Dt:
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06/22/2001
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Publication #:
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Pub Dt:
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12/26/2002
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Title:
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METHOD FOR FORMING A SINGLE WIRING LEVEL FOR TRANSISTORS WITH PLANAR AND VERTICAL GATES ON THE SAME SUBSTRATE
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Patent #:
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Issue Dt:
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05/20/2003
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Application #:
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09893157
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Filing Dt:
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06/27/2001
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Publication #:
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Pub Dt:
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01/02/2003
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Title:
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ETCH SELECTIVITY INVERSION FOR ETCHING ALONG CRYSTALLOGRAPHIC DIRECTIONS IN SILICON
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Patent #:
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Issue Dt:
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08/20/2002
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Application #:
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09900626
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Filing Dt:
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07/06/2001
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Title:
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DRAM REFRESH TIMING ADJUSTMENT DEVICE, SYSTEM AND METHOD
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Patent #:
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Issue Dt:
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04/15/2003
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Application #:
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09900649
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Filing Dt:
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07/06/2001
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Publication #:
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Pub Dt:
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01/09/2003
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Title:
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MEMORY CELL, MEMORY CELL ARRANGEMENT AND FABRICATION METHOD
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Patent #:
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Issue Dt:
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03/11/2003
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Application #:
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09904799
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Filing Dt:
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07/13/2001
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Publication #:
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Pub Dt:
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01/16/2003
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Title:
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METHOD FOR HIGH ASPECT RATIO GAP FILL USING SEQUENTIAL HDP-CVD
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Patent #:
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Issue Dt:
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01/13/2004
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Application #:
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09906886
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Filing Dt:
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07/17/2001
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Publication #:
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Pub Dt:
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01/23/2003
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Title:
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PROGRAMMABLE TEST SOCKET
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Patent #:
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Issue Dt:
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06/17/2003
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Application #:
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09907894
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Filing Dt:
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07/17/2001
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Publication #:
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Pub Dt:
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01/23/2003
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Title:
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SOLDER-FREE PCB ASSEMBLY
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Patent #:
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Issue Dt:
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07/29/2003
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Application #:
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09910771
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Filing Dt:
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07/24/2001
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Publication #:
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Pub Dt:
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01/30/2003
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Title:
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METHOD OF PREPARING BURIED LOCOS COLLAR IN TRENCH DRAMS
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Patent #:
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Issue Dt:
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02/03/2004
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Application #:
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09917867
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Filing Dt:
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07/26/2001
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Publication #:
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Pub Dt:
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09/19/2002
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Title:
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METHOD FOR PRODUCING METALLIC BIT LINES FOR MEMORY CELL ARRAYS, METHOD FOR PRODUCING MEMORY CELL ARRAYS AND MEMORY CELL ARRAY
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Patent #:
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Issue Dt:
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07/27/2004
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Application #:
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09918353
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Filing Dt:
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07/30/2001
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Publication #:
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Pub Dt:
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01/30/2003
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Title:
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DELIVERING DATA OPTICALLY TO AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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11/01/2005
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Application #:
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09918933
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Filing Dt:
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07/30/2001
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Publication #:
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Pub Dt:
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01/30/2003
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Title:
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RECORDING TEST INFORMATION TO IDENTIFY MEMORY CELL ERRORS
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Patent #:
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Issue Dt:
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03/18/2003
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Application #:
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09930690
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Filing Dt:
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08/15/2001
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Publication #:
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Pub Dt:
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02/20/2003
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Title:
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PROCESS FLOW FOR SACRIFICIAL COLLAR SCHEME WITH VERTICAL NITRIDE MASK
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Patent #:
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Issue Dt:
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12/30/2003
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Application #:
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09939554
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Filing Dt:
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08/28/2001
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Title:
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PROCESS FLOW FOR TWO-STEP COLLAR IN DRAM PREPARATION
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Patent #:
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Issue Dt:
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10/01/2002
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Application #:
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09940761
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Filing Dt:
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08/27/2001
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Title:
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PROCESS FLOW FOR SACRIFICIAL COLLAR WITH POLY MASK
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Patent #:
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Issue Dt:
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12/16/2003
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Application #:
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09944796
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Filing Dt:
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08/31/2001
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Publication #:
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Pub Dt:
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03/06/2003
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Title:
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PAD- REROUTING FOR INTEGRATED CIRCUIT CHIPS
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Patent #:
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Issue Dt:
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06/18/2002
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Application #:
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09945007
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Filing Dt:
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08/31/2001
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Title:
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BURIED STRAP FORMATION WITHOUT TTO DEPOSITION
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Patent #:
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Issue Dt:
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01/21/2003
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Application #:
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09952839
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Filing Dt:
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09/14/2001
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Title:
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METHOD FOR FORMING STRUCTURES ON A WAFER
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Patent #:
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Issue Dt:
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03/23/2004
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Application #:
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09965093
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Filing Dt:
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09/28/2001
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Publication #:
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Pub Dt:
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04/03/2003
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Title:
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DIRECT, NON-DESTRUCTIVE MEASUREMENT OF RECESS DEPTH IN A WAFER
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Patent #:
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Issue Dt:
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10/15/2002
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Application #:
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09966332
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Filing Dt:
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09/28/2001
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Title:
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METHOD OF FORMING A SELF-ALIGNED ANTIFUSE LINK
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Patent #:
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Issue Dt:
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01/11/2005
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Application #:
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09966506
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Filing Dt:
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09/28/2001
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Publication #:
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Pub Dt:
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04/03/2003
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Title:
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OPTICAL MEASUREMENT OF PLANARIZED FEATURES
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Patent #:
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Issue Dt:
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12/27/2005
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Application #:
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09967008
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Filing Dt:
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09/28/2001
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Publication #:
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Pub Dt:
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04/03/2003
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Title:
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MEMORY AND METHOD FOR EMPLOYING A CHECKSUM FOR ADDRESSES OF REPLACED STORAGE ELEMENTS
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Patent #:
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Issue Dt:
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04/20/2004
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Application #:
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09967176
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Filing Dt:
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09/28/2001
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Publication #:
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Pub Dt:
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04/03/2003
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Title:
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METHOD FOR OVERLAY METROLOGY OF LOW CONTRAST FEATURES
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Patent #:
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Issue Dt:
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10/04/2005
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Application #:
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09967225
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Filing Dt:
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09/28/2001
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Publication #:
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Pub Dt:
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04/03/2003
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Title:
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METHOD FOR FORMING INSIDE NITRIDE SPACER FOR DEEP TRENCH DEVICE DRAM CELL
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Patent #:
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Issue Dt:
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10/05/2004
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Application #:
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09967299
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Filing Dt:
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09/28/2001
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Publication #:
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Pub Dt:
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04/03/2003
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Title:
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ALIGNMENT SYSTEM AND METHOD USING BRIGHT SPOT AND BOX STRUCTURE
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Patent #:
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Issue Dt:
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12/09/2003
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Application #:
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09967318
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Filing Dt:
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09/28/2001
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Publication #:
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Pub Dt:
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04/03/2003
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Title:
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PROCESS FOR CHEMICAL MECHANICAL POLISHING
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Patent #:
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Issue Dt:
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03/15/2005
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Application #:
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09988183
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Filing Dt:
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11/19/2001
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Publication #:
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Pub Dt:
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05/22/2003
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Title:
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FORMATION OF DUAL WORK FUNCTION GATE ELECTRODE
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Issue Dt:
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11/16/2004
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Application #:
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10000690
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11/15/2001
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Publication #:
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Pub Dt:
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05/15/2003
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Title:
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DATA PROCESSING SYSTEM HAVING CONFIGURABLE COMPONENTS
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Patent #:
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Issue Dt:
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12/21/2004
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Application #:
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10002396
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Filing Dt:
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10/23/2001
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Publication #:
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Pub Dt:
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04/24/2003
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Title:
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SIMULTANEOUS BIDIRECTIONAL SIGNAL TRANSMISSION
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Patent #:
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Issue Dt:
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04/15/2003
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Application #:
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10015212
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Filing Dt:
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12/10/2001
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Title:
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METHOD FOR ENABLING ACCESS TO MICRO-SECTIONS OF INTEGRATED CIRCUITS ON A WAFER
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Patent #:
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Issue Dt:
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08/24/2004
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Application #:
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10032876
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Filing Dt:
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10/24/2001
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Publication #:
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Pub Dt:
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04/24/2003
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Title:
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GRAPHICAL USER INTERFACE FOR TESTING INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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05/03/2005
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Application #:
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10032941
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Filing Dt:
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10/31/2001
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Publication #:
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Pub Dt:
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05/01/2003
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Title:
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COMPLIANT RELIEF WAFER LEVEL PACKAGING
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Patent #:
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Issue Dt:
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12/02/2003
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Application #:
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10033877
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Filing Dt:
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12/27/2001
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Publication #:
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Pub Dt:
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07/11/2002
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Title:
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CURRENT MIRROR CIRCUIT
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Patent #:
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Issue Dt:
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04/08/2003
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Application #:
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10041779
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Filing Dt:
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10/19/2001
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Publication #:
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Pub Dt:
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04/24/2003
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Title:
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PROCESS FLOW FOR SACRIFICIAL COLLAR WITH POLYSILICON VOID
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Patent #:
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Issue Dt:
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04/27/2004
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Application #:
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10044000
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Filing Dt:
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10/31/2001
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Publication #:
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Pub Dt:
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05/01/2003
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Title:
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TRANSFER WAFER LEVEL PACKAGING
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Patent #:
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Issue Dt:
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10/28/2003
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Application #:
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10044136
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Filing Dt:
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01/10/2002
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Publication #:
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Pub Dt:
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07/10/2003
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Title:
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FORMING A STRUCTURE ON A WAFER
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Patent #:
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Issue Dt:
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06/24/2003
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Application #:
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10047824
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Filing Dt:
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01/15/2002
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Publication #:
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Pub Dt:
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07/18/2002
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Title:
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SEMICONDUCTOR MEMORY HAVING A DELAY LOCKED LOOP
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Patent #:
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Issue Dt:
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02/03/2004
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Application #:
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10050737
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Filing Dt:
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01/16/2002
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Publication #:
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Pub Dt:
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07/17/2003
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Title:
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METHOD FOR MONITORING THE RATE OF ETCHING OF A SEMICONDUCTOR
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Patent #:
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Issue Dt:
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04/20/2004
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Application #:
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10051544
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Filing Dt:
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01/18/2002
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Publication #:
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Pub Dt:
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07/24/2003
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Title:
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SYSTEM AND METHOD FOR BACK-SIDE CONTACT FOR TRENCH SEMICONDUCTOR DEVICE CHARACTERIZATION
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Patent #:
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Issue Dt:
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04/01/2003
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Application #:
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10052201
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Filing Dt:
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01/17/2002
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Title:
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PROCESS FOR IMPLEMENTATION OF A HARDMASK
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Patent #:
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Issue Dt:
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03/23/2004
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Application #:
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10053970
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Filing Dt:
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01/22/2002
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Publication #:
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Pub Dt:
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07/25/2002
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Title:
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TEST CIRCUIT FOR AN ANALOG MEASUREMENT OF BIT LINE SIGNALS OF FERROELECTRIC MEMORY CELLS
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Patent #:
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Issue Dt:
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09/09/2003
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Application #:
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10057065
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Filing Dt:
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01/25/2002
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Publication #:
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Pub Dt:
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07/31/2003
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Title:
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METHOD FOR ACHIEVING HIGH SELF-ALIGNING VERTICAL GATE STUDS RELATIVE TO THE SUPPORT ISOLATION LEVEL
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Patent #:
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Issue Dt:
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12/13/2005
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Application #:
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10057500
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Filing Dt:
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01/25/2002
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Title:
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GENERATING AN EXECUTABLE FILE
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Patent #:
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Issue Dt:
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03/23/2004
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Application #:
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10062942
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Filing Dt:
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01/31/2002
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Publication #:
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Pub Dt:
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07/31/2003
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Title:
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METHOD OF APPLYING A BOTTOM SURFACE PROTECTIVE COATING TO A WAFER, AND WAFER DICING METHOD
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Issue Dt:
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12/30/2003
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Application #:
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10074479
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Filing Dt:
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02/11/2002
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Publication #:
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Pub Dt:
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08/14/2003
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Title:
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MASK AND METHOD FOR PATTERNING A SEMICONDUCTOR WAFER
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Patent #:
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Issue Dt:
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11/04/2003
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Application #:
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10074578
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Filing Dt:
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02/13/2002
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Publication #:
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Pub Dt:
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09/05/2002
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Title:
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OSCILLATOR CIRCUIT
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Patent #:
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Issue Dt:
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11/29/2005
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Application #:
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10075539
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Filing Dt:
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02/14/2002
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Publication #:
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Pub Dt:
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09/26/2002
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Title:
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DDR TO SDR CONVERSION THAT DECODES READ AND WRITE ACCESSES AND FORWARDS DELAYED COMMANDS TO FIRST AND SECOND MEMORY MODULES
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Patent #:
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Issue Dt:
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05/27/2003
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Application #:
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10075540
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Filing Dt:
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02/14/2002
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Publication #:
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Pub Dt:
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09/12/2002
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Title:
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METHOD FOR PRODUCING AN ALTERNATING PHASE MASK
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Patent #:
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Issue Dt:
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03/30/2004
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Application #:
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10075582
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Filing Dt:
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02/14/2002
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Publication #:
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Pub Dt:
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08/14/2003
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Title:
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METHOD FOR SIMULATING AN ELECTRICAL CIRCUIT, COMPUTER PROGRAM PRODUCT, SOFTWARE APPLICATION, AND DATA CARRIER
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Patent #:
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Issue Dt:
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08/10/2004
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Application #:
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10076977
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Filing Dt:
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02/15/2002
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Publication #:
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Pub Dt:
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08/15/2002
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Title:
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TEST SYSTEM FOR CONDUCTING A FUNCTION TEST OF A SEMICONDUCTOR ELEMENT ON A WAFER, AND OPERATING METHOD
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Patent #:
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Issue Dt:
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06/17/2003
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Application #:
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10077518
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Filing Dt:
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02/15/2002
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Title:
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DUAL GATE OXIDE PROCESS WITHOUT CRITICAL RESIST AND WITHOUT N2 IMPLANT
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Patent #:
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Issue Dt:
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10/01/2002
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Application #:
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10079045
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Filing Dt:
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02/19/2002
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Publication #:
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Pub Dt:
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10/24/2002
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Title:
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METHOD FOR FABRICATING AN INTEGRATED CIRCUIT, IN PARTICULAR AN ANTIFUSE
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Patent #:
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Issue Dt:
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11/11/2003
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Application #:
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10082552
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Filing Dt:
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02/25/2002
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Publication #:
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Pub Dt:
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08/29/2002
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Title:
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MEASUREMENT TECHNIQUE FOR DETERMINING THE WIDTH OF A STRUCTURE ON A MASK
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Patent #:
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Issue Dt:
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04/01/2003
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Application #:
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10082553
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Filing Dt:
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02/25/2002
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Publication #:
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Pub Dt:
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08/29/2002
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Title:
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INTEGRATED DRAM MEMORY MODULE
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Patent #:
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Issue Dt:
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09/13/2005
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Application #:
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10084194
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Filing Dt:
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02/28/2002
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Publication #:
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Pub Dt:
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12/09/2004
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Title:
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INTEGRATION SCHEME FOR METAL GAP FILL, WITH FIXED ABRASIVE CMP
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Patent #:
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Issue Dt:
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05/27/2003
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Application #:
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10090278
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Filing Dt:
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03/04/2002
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Publication #:
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Pub Dt:
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09/05/2002
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Title:
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VOLTAGE GENERATOR WITH STANDBY OPERATING MODE
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Patent #:
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Issue Dt:
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11/04/2003
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Application #:
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10090306
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Filing Dt:
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03/04/2002
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Publication #:
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Pub Dt:
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09/05/2002
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Title:
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INTEGRATED MEMORY HAVING A PLURALITY OF MEMORY CELL ARRAYS
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Patent #:
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Issue Dt:
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10/18/2005
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Application #:
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10092129
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Filing Dt:
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03/06/2002
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Publication #:
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Pub Dt:
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11/14/2002
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Title:
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ADDRESS GENERATOR FOR GENERATING ADDRESSES FOR TESTING A CIRCUIT
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Patent #:
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Issue Dt:
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05/11/2004
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Application #:
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10094890
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Filing Dt:
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03/06/2002
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Publication #:
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Pub Dt:
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09/12/2002
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Title:
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METHOD AND SEMICONDUCTOR COMPONENT HAVING A DEVICE FOR DETERMINING AN INTERNAL VOLTAGE
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Patent #:
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Issue Dt:
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10/28/2003
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Application #:
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10096459
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Filing Dt:
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03/12/2002
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Publication #:
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Pub Dt:
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09/12/2002
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Title:
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METHOD FOR PRODUCING A MEMORY CELL FOR A SEMICONDUCTOR MEMORY
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Patent #:
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Issue Dt:
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05/20/2003
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Application #:
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10096473
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Filing Dt:
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03/12/2002
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Publication #:
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Pub Dt:
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09/12/2002
| | | | |
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Title:
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METHOD FOR PRODUCING A CELL OF A SEMICONDUCTOR MEMORY
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Patent #:
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Issue Dt:
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09/02/2003
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Application #:
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10097509
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Filing Dt:
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03/14/2002
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Publication #:
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Pub Dt:
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09/26/2002
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Title:
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METHOD FOR FABRICATING AN INTEGRATED FERROELECTRIC SEMICONDUCTOR MEMORY AND INTEGRATED FERROELECTRIC SEMICONDUCTOR MEMORY
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Patent #:
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Issue Dt:
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12/02/2003
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Application #:
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10098273
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Filing Dt:
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03/15/2002
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Publication #:
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Pub Dt:
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09/18/2003
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Title:
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SEMICONDUCTOR WAFER TESTING SYSTEM AND METHOD
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Patent #:
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Issue Dt:
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09/25/2007
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Application #:
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10098845
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Filing Dt:
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03/14/2002
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Publication #:
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Pub Dt:
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09/19/2002
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Title:
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METHOD FOR PRODUCING A POROUS COATING
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Patent #:
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Issue Dt:
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07/22/2003
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Application #:
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10100467
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Filing Dt:
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03/18/2002
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Publication #:
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Pub Dt:
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12/12/2002
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Title:
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CIRCUIT ARRANGEMENT FOR SCALABLE OUTPUT DRIVERS
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Patent #:
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Issue Dt:
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06/01/2004
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Application #:
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10100504
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Filing Dt:
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03/18/2002
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Publication #:
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Pub Dt:
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11/21/2002
| | | | |
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Title:
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TEST CIRCUIT
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Patent #:
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Issue Dt:
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12/31/2002
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Application #:
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10100812
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Filing Dt:
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03/19/2002
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Publication #:
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Pub Dt:
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09/19/2002
| | | | |
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Title:
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METHOD FOR MANUFACTURING A TRENCH CAPACITOR OF A MEMORY CELL OF A SEMICONDUCTOR MEMORY
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Patent #:
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Issue Dt:
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11/25/2003
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Application #:
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10103009
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Filing Dt:
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03/21/2002
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Publication #:
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Pub Dt:
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10/17/2002
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Title:
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METHOD OF PROVIDING TRENCH WALLS BY USING TWO-STEP ETCHING PROCESSES
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Patent #:
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Issue Dt:
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04/06/2004
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Application #:
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10103373
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Filing Dt:
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03/21/2002
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Publication #:
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Pub Dt:
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09/26/2002
| | | | |
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Title:
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SEMICONDUCTOR MODULE
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Patent #:
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Issue Dt:
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10/10/2006
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Application #:
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10103517
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Filing Dt:
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03/22/2002
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Publication #:
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Pub Dt:
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09/26/2002
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Title:
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METHOD AND DEVICE FOR DATA TRANSFER
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Patent #:
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Issue Dt:
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10/28/2003
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Application #:
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10105547
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Filing Dt:
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03/25/2002
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Publication #:
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Pub Dt:
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09/26/2002
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Title:
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SEMICONDUCTOR MEMORY WITH REFRESH AND METHOD FOR OPERATING THE SEMICONDUCTOR MEMORY
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Patent #:
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Issue Dt:
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02/17/2004
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Application #:
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10105878
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Filing Dt:
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03/25/2002
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Publication #:
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Pub Dt:
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11/21/2002
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Title:
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METHOD AND DEVICE FOR DETERMINING AN OPERATING TEMPERATURE OF A SEMICONDUCTOR COMPONENT
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Patent #:
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Issue Dt:
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10/03/2006
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Application #:
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10106414
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Filing Dt:
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03/26/2002
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Publication #:
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Pub Dt:
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01/02/2003
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Title:
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TEST CIRCUIT FOR TESTING A SYNCHRONOUS MEMORY CIRCUIT
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Patent #:
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Issue Dt:
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01/24/2006
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Application #:
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10108359
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Filing Dt:
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03/29/2002
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Publication #:
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Pub Dt:
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10/02/2003
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Title:
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PRODUCING LOW K INTER-LAYER DIELECTRIC FILMS USING SI-CONTAINING RESISTS
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Patent #:
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Issue Dt:
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12/07/2004
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Application #:
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10109545
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Filing Dt:
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03/28/2002
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Publication #:
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Pub Dt:
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04/10/2003
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Title:
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METHOD FOR CLASSIFYING COMPONENTS
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Patent #:
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Issue Dt:
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03/08/2005
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Application #:
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10109657
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Filing Dt:
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04/01/2002
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Publication #:
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Pub Dt:
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10/24/2002
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Title:
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TEST DATA GENERATOR
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Patent #:
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Issue Dt:
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07/08/2003
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Application #:
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10112521
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Filing Dt:
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03/28/2002
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Publication #:
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Pub Dt:
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10/03/2002
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Title:
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DYNAMIC SEMICONDUCTOR MEMORY WITH REFRESH AND METHOD FOR OPERATING SUCH A MEMORY
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Patent #:
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Issue Dt:
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03/16/2004
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Application #:
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10113413
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Filing Dt:
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04/01/2002
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Publication #:
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Pub Dt:
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10/03/2002
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Title:
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INTEGRATED DYNAMIC MEMORY DEVICE AND METHOD FOR OPERATING AN INTEGRATED DYNAMIC MEMORY
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Patent #:
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Issue Dt:
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11/11/2003
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Application #:
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10113415
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Filing Dt:
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04/01/2002
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Publication #:
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Pub Dt:
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10/03/2002
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Title:
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INTEGRATED MEMORY CHIP WITH A DYNAMIC MEMORY
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Patent #:
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Issue Dt:
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11/09/2004
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Application #:
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10114484
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Filing Dt:
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04/03/2002
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Publication #:
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Pub Dt:
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10/09/2003
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Title:
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ELIMINATION OF RESIST FOOTING ON TERA HARDMASK
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Patent #:
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Issue Dt:
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08/19/2003
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Application #:
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10114772
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Filing Dt:
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04/02/2002
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Publication #:
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Pub Dt:
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10/03/2002
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Title:
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CIRCUIT CONFIGURATION FOR CONTROLLING THE WORD LINES OF A MEMORY MATRIX
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Patent #:
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Issue Dt:
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08/29/2006
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10114773
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04/02/2002
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Publication #:
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Pub Dt:
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10/03/2002
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Title:
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METHOD AND CONFIGURATION FOR CONDITIONING A POLISHING PAD SURFACE
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03/08/2005
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10114796
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04/02/2002
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Pub Dt:
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10/03/2002
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Title:
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METHOD FOR CALCULATING THE CAPACITY OF A LAYOUT OF AN INTEGRATED CIRCUIT WITH THE AID OF A COMPUTER, AND APPLICATION OF THE METHOD TO INTEGRATED CIRCUIT FABRICATION
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09/02/2003
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10116826
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04/05/2002
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Pub Dt:
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10/10/2002
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Title:
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CIRCUIT CONFIGURATION WITH A MEMORY ARRAY
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Issue Dt:
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02/10/2004
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10117826
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04/08/2002
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Pub Dt:
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10/10/2002
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Title:
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METHOD OF SIMULTANEOUSLY POLISHING A PLURALITY OF OBJECTS OF A SIMILAR TYPE, IN PARTICULAR SILICON WAFERS, ON A POLISHING INSTALLATION
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Patent #:
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Issue Dt:
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11/11/2003
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Application #:
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10119607
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04/10/2002
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Publication #:
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Pub Dt:
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10/10/2002
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Title:
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INTEGRATED CLOCK GENERATOR, PARTICULARLY FOR DRIVING A SEMICONDUCTOR MEMORY WITH A TEST SIGNAL
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Patent #:
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Issue Dt:
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05/25/2004
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Application #:
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10122996
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04/12/2002
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Pub Dt:
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10/16/2003
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Title:
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ETCH PROCESS FOR RECESSING POLYSILICON IN TRENCH STRUCTURES
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Issue Dt:
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06/03/2003
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Application #:
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10125088
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04/18/2002
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Pub Dt:
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10/24/2002
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Title:
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CIRCUIT CONFIGURATION FOR ENABLING A CLOCK SIGNAL IN A MANNER DEPENDENT ON AN ENABLE SIGNAL
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Issue Dt:
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10/28/2003
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Application #:
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10125089
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Filing Dt:
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04/18/2002
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Pub Dt:
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10/24/2002
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Title:
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INTEGRATED MEMORY AND METHOD FOR TESTING AN INTEGRATED MEMORY
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05/04/2004
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Application #:
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10126371
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04/19/2002
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Pub Dt:
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10/24/2002
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Title:
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METHOD FOR DETERMINING AND REMOVING PHASE CONFLICTS ON ALTERNATING PHASE MASKS
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Issue Dt:
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11/13/2007
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Application #:
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10126376
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04/19/2002
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Publication #:
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Pub Dt:
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10/24/2002
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Title:
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METHOD FOR TESTING SEMICONDUCTOR MEMORY MODULES
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Issue Dt:
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06/24/2003
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Application #:
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10128068
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04/23/2002
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Pub Dt:
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12/19/2002
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Title:
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INTEGRATED CIRCUIT WITH ACTIVE REGIONS HAVING VARYING CONTACT ARRANGEMENTS
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06/01/2004
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Application #:
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10132388
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04/26/2002
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Pub Dt:
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10/31/2002
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Title:
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DATA REGISTER WITH INTEGRATED SIGNAL LEVEL CONVERSION
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Issue Dt:
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05/22/2007
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10133795
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04/26/2002
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Pub Dt:
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12/12/2002
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Title:
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METHOD FOR REPAIRING HARDWARE FAULTS IN MEMORY CHIPS
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12/12/2006
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10134023
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04/26/2002
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Publication #:
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Pub Dt:
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01/02/2003
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Title:
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METHOD OF TESTING THE DATA EXCHANGE FUNCTIONALITY OF A MEMORY
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