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Patent #:
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Issue Dt:
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06/08/2004
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Application #:
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10134104
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Filing Dt:
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04/29/2002
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Publication #:
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Pub Dt:
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10/31/2002
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Title:
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PROCESS FOR STRUCTURING A PHOTORESIST LAYER
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Patent #:
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Issue Dt:
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06/08/2004
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Application #:
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10134105
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Filing Dt:
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04/29/2002
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Publication #:
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Pub Dt:
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10/31/2002
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Title:
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PROCESS FOR STRUCTURING A PHOTORESIST LAYER
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Patent #:
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Issue Dt:
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01/27/2004
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Application #:
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10134106
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Filing Dt:
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04/29/2002
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Publication #:
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Pub Dt:
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12/05/2002
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Title:
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METHOD FOR CONTROLLING A PROCESSING DEVICE FOR A SEQUENTIAL PROCESSING OF SEMICONDUCTOR WAFERS
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Patent #:
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Issue Dt:
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05/03/2005
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Application #:
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10134146
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Filing Dt:
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04/29/2002
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Publication #:
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Pub Dt:
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10/31/2002
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Title:
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METHOD FOR STRUCTURING A PHOTORESIST LAYER
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Patent #:
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Issue Dt:
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05/25/2004
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Application #:
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10134151
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Filing Dt:
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04/29/2002
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Publication #:
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Pub Dt:
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10/31/2002
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Title:
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METHOD FOR STRUCTURING A PHOTORESIST LAYER
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Patent #:
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Issue Dt:
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08/10/2004
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Application #:
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10134152
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Filing Dt:
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04/29/2002
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Publication #:
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Pub Dt:
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10/31/2002
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Title:
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CIRCUIT FOR SYNCHRONIZING SIGNALS DURING THE EXCHANGE OF INFORMATION BETWEEN CIRCUITS
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Patent #:
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Issue Dt:
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04/20/2004
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Application #:
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10134670
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Filing Dt:
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04/29/2002
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Publication #:
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Pub Dt:
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11/21/2002
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Title:
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DATA MEMORY
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Patent #:
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Issue Dt:
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10/19/2004
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Application #:
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10134893
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Filing Dt:
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04/29/2002
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Publication #:
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Pub Dt:
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10/31/2002
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Title:
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HOLDER FOR SEMICONDUCTOR WAFERS IN A BRUSH-CLEANING INSTALLATION
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Patent #:
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Issue Dt:
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03/01/2005
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Application #:
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10135273
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Filing Dt:
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04/30/2002
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Publication #:
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Pub Dt:
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10/30/2003
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Title:
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METHOD PRODUCING A CONTACT CONNECTION BETWEEN A SEMICONDUCTOR CHIP AND A SUBSTRATE AND THE CONTACT CONNECTION
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Patent #:
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Issue Dt:
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08/24/2004
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Application #:
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10135416
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Filing Dt:
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04/30/2002
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Publication #:
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Pub Dt:
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10/31/2002
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Title:
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MRAM SEMICONDUCTOR MEMORY CONFIGURATION WITH REDUNDANT CELL ARRAYS
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Patent #:
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Issue Dt:
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02/24/2004
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Application #:
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10135471
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Filing Dt:
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04/30/2002
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Publication #:
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Pub Dt:
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03/20/2003
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Title:
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METHOD FOR EXPERIMENTALLY VERIFYING IMAGING ERRORS IN OPTICAL EXPOSURE UNITS
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Patent #:
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Issue Dt:
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10/05/2004
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Application #:
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10135684
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Filing Dt:
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04/30/2002
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Publication #:
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Pub Dt:
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01/16/2003
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Title:
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METHOD FOR EXPERIMENTALLY VERIFYING IMAGING ERRORS IN PHOTOMASKS
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Patent #:
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Issue Dt:
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04/18/2006
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Application #:
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10135686
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Filing Dt:
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04/30/2002
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Publication #:
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Pub Dt:
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11/28/2002
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Title:
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METHOD AND DEVICE FOR INITIALISING AN ASYNCHRONOUS LATCH CHAIN
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Patent #:
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Issue Dt:
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09/09/2003
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Application #:
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10137125
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Filing Dt:
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05/02/2002
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Publication #:
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Pub Dt:
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12/26/2002
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Title:
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TEST CIRCUIT FOR TESTING A CIRCUIT
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Patent #:
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Issue Dt:
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06/28/2005
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Application #:
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10137511
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Filing Dt:
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04/30/2002
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Publication #:
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Pub Dt:
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07/29/2004
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Title:
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INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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11/11/2003
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Application #:
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10139165
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Filing Dt:
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05/06/2002
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Publication #:
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Pub Dt:
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01/16/2003
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Title:
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METHOD FOR IMPROVING A DOPING PROFILE FOR GAS PHASE DOPING
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Patent #:
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Issue Dt:
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10/21/2003
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Application #:
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10139168
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Filing Dt:
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05/06/2002
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Publication #:
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Pub Dt:
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11/07/2002
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Title:
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MEMORY CIRCUIT HAVING A PLURALITY OF MEMORY AREAS
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Patent #:
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Issue Dt:
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04/17/2007
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Application #:
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10139835
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Filing Dt:
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05/07/2002
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Publication #:
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Pub Dt:
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11/28/2002
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Title:
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METHOD AND APPARATUS FOR CALIBRATING A TEST SYSTEM FOR AN INTEGRATED SEMICONDUCTOR CIRCUIT
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Patent #:
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Issue Dt:
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06/06/2006
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Application #:
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10143600
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Filing Dt:
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05/10/2002
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Publication #:
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Pub Dt:
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11/28/2002
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Title:
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METHOD AND APPARATUS FOR GENERATING A SECOND SIGNAL HAVING A CLOCK BASED ON A SECOND CLOCK FROM A FIRST SIGNAL HAVING A FIRST CLOCK
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Patent #:
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Issue Dt:
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01/04/2005
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Application #:
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10143627
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Filing Dt:
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05/10/2002
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Publication #:
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Pub Dt:
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11/14/2002
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Title:
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CIRCUIT MODULE
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Patent #:
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Issue Dt:
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04/18/2006
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Application #:
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10145393
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Filing Dt:
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05/14/2002
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Publication #:
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Pub Dt:
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12/12/2002
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Title:
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WIRING PROCESS
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Patent #:
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Issue Dt:
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02/03/2004
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Application #:
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10145579
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Filing Dt:
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05/14/2002
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Publication #:
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Pub Dt:
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11/28/2002
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Title:
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APPARATUS AND METHOD FOR REDUCING REFLEXIONS IN A MEMORY BUS SYSTEM
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Patent #:
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Issue Dt:
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03/29/2005
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Application #:
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10147543
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Filing Dt:
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05/16/2002
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Publication #:
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Pub Dt:
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12/19/2002
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Title:
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METHOD FOR FABRICATING A LITHOGRAPHIC REFLECTION MASK IN PARTICULAR FOR THE PATTERNING OF A SEMICONDUCTOR WAFER, AND A REFLECTION MASK
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Patent #:
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Issue Dt:
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01/24/2006
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Application #:
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10147544
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Filing Dt:
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05/16/2002
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Publication #:
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Pub Dt:
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11/21/2002
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Title:
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METHOD FOR FABRICATING A TRENCH CONTACT TO A DEEP TRENCH CAPACITOR HAVING A POLYSILICON FILLING
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Patent #:
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Issue Dt:
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10/11/2005
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Application #:
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10147545
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Filing Dt:
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05/16/2002
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Publication #:
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Pub Dt:
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11/21/2002
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Title:
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METHOD OF MATCHING DIFFERENT SIGNAL PROPAGATION TIMES BETWEEN A CONTROLLER AND AT LEAST TWO PROCESSING UNITS, AND A COMPUTER SYSTEM
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Patent #:
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Issue Dt:
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04/13/2004
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Application #:
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10150340
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Filing Dt:
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05/17/2002
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Publication #:
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Pub Dt:
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01/16/2003
| | | | |
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Title:
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METHOD AND CIRCUIT ARRANGEMENT FOR READING OUT AND FOR STORING BINARY MEMORY CELL SIGNALS
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Patent #:
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Issue Dt:
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04/27/2004
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Application #:
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10151088
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Filing Dt:
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05/20/2002
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Publication #:
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Pub Dt:
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11/21/2002
| | | | |
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Title:
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INTEGRATED MEMORY
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Patent #:
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Issue Dt:
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05/24/2005
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Application #:
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10151989
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Filing Dt:
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05/21/2002
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Publication #:
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Pub Dt:
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11/21/2002
| | | | |
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Title:
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METHOD AND DEVICE FOR TESTING A MEMORY CIRCUIT
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Patent #:
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Issue Dt:
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02/22/2005
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Application #:
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10151990
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Filing Dt:
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05/21/2002
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Publication #:
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Pub Dt:
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03/27/2003
| | | | |
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Title:
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METHOD FOR TESTING SEMICONDUCTOR CHIPS
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Patent #:
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Issue Dt:
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11/25/2003
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Application #:
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10152950
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Filing Dt:
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05/21/2002
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Publication #:
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Pub Dt:
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01/09/2003
| | | | |
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Title:
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METHOD FOR READING AND STORING BINARY MEMORY CELL SIGNALS AND CIRCUIT ARRANGEMENT
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Patent #:
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Issue Dt:
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06/01/2004
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Application #:
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10153766
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Filing Dt:
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05/22/2002
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Publication #:
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Pub Dt:
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02/20/2003
| | | | |
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Title:
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SEMICONDUCTOR MEMORY WITH JOINTLY USABLE FUSES
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Patent #:
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Issue Dt:
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12/30/2003
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Application #:
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10154343
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Filing Dt:
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05/23/2002
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Publication #:
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Pub Dt:
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11/28/2002
| | | | |
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Title:
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SEMICONDUCTOR CHIP WITH TRIMMABLE OSCILLATOR
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Patent #:
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Issue Dt:
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05/15/2007
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Application #:
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10154476
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Filing Dt:
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05/22/2002
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Publication #:
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Pub Dt:
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04/03/2003
| | | | |
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Title:
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BUILT OFF SELF TEST (BOST) IN THE KERF
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Patent #:
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Issue Dt:
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06/29/2004
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Application #:
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10155337
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Filing Dt:
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05/24/2002
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Publication #:
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Pub Dt:
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02/20/2003
| | | | |
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Title:
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SELF-ADHERING CHIP
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Patent #:
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Issue Dt:
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02/24/2004
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Application #:
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10156482
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Filing Dt:
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05/28/2002
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Publication #:
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Pub Dt:
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11/28/2002
| | | | |
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Title:
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SEMICONDUCTOR SUBSTRATE HOLDER FOR CHEMICAL-MECHANICAL POLISHING CONTAINING A MOVABLE PLATE
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Patent #:
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Issue Dt:
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05/18/2004
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Application #:
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10156536
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Filing Dt:
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05/28/2002
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Publication #:
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Pub Dt:
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11/28/2002
| | | | |
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Title:
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MEMORY MODULE HAVING A MEMORY CELL AND METHOD FOR FABRICATING THE MEMORY MODULE
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Patent #:
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Issue Dt:
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01/11/2005
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Application #:
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10156538
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Filing Dt:
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05/28/2002
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Publication #:
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Pub Dt:
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11/28/2002
| | | | |
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Title:
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IMAGING SYSTEM AND METHOD FOR POSITIONING A MEASURING TIP ONTO A CONTACT REGION OF A MICROCHIP
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Patent #:
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Issue Dt:
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09/30/2003
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Application #:
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10157726
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Filing Dt:
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05/29/2002
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Publication #:
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Pub Dt:
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12/05/2002
| | | | |
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Title:
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DATA OUTPUT INTERFACE, IN PARTICULAR FOR SEMICONDUCTOR MEMORIES
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Patent #:
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Issue Dt:
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09/28/2004
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Application #:
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10157870
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Filing Dt:
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05/31/2002
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Publication #:
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Pub Dt:
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12/04/2003
| | | | |
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Title:
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PROCESS OF FABRICATING DRAM CELLS WITH COLLAR ISOLATION LAYERS
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Patent #:
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Issue Dt:
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10/28/2003
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Application #:
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10158031
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Filing Dt:
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05/30/2002
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Publication #:
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Pub Dt:
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12/19/2002
| | | | |
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Title:
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MEMORY CHIP HAVING A TEST MODE AND METHOD FOR CHECKING MEMORY CELLS OF A REPAIRED MEMORY CHIP
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Patent #:
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Issue Dt:
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02/17/2004
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Application #:
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10158267
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Filing Dt:
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05/30/2002
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Publication #:
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Pub Dt:
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12/05/2002
| | | | |
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Title:
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METHOD AND DEVICE FOR MEASURING THE PHASE SHIFT BETWEEN A PERIODIC SIGNAL AND AN OUTPUT SIGNAL AT AN OUTPUT OF AN ELECTRONIC COMPONENT
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Patent #:
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Issue Dt:
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07/29/2003
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Application #:
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10158271
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Filing Dt:
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05/30/2002
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Publication #:
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Pub Dt:
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12/05/2002
| | | | |
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Title:
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METHOD AND DEVICE FOR MEASURING A TEMPERATURE IN AN ELECTRONIC COMPONENT
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Patent #:
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Issue Dt:
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04/27/2004
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Application #:
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10158275
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Filing Dt:
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05/30/2002
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Publication #:
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Pub Dt:
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12/05/2002
| | | | |
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Title:
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SEMICONDUCTOR MEMORY WITH A SIGNAL PATH
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Patent #:
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Issue Dt:
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02/25/2003
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Application #:
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10158465
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Filing Dt:
|
05/30/2002
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Publication #:
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Pub Dt:
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12/05/2002
| | | | |
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Title:
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METHOD FOR FABRICATING AN INTEGRATED CIRCUIT WITH UNDERCUT ETCHING
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|
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Patent #:
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Issue Dt:
|
06/03/2003
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Application #:
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10158982
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Filing Dt:
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05/30/2002
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Title:
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ISOLATING A VERTICAL GATE CONTACT STRUCTURE
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Patent #:
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Issue Dt:
|
04/20/2004
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Application #:
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10159155
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Filing Dt:
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05/31/2002
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Publication #:
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Pub Dt:
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02/20/2003
| | | | |
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Title:
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METHOD FOR FABRICATING A GATE STACK IN VERY LARGE SCALE INTEGRATED SEMICONDUCTOR MEMORIES
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|
|
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Patent #:
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Issue Dt:
|
09/02/2003
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Application #:
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10159156
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Filing Dt:
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05/31/2002
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Publication #:
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Pub Dt:
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12/26/2002
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Title:
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MEMORY ELEMENT WITH MOLECULAR OR POLYMERIC LAYERS, MEMORY CELL, MEMORY ARRAY, AND SMART CARD
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Patent #:
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Issue Dt:
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08/10/2004
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Application #:
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10159261
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Filing Dt:
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05/31/2002
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Publication #:
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Pub Dt:
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12/19/2002
| | | | |
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Title:
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MEMORY CELL ARRANGEMENT AND METHOD FOR ITS FABRICATION
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Patent #:
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Issue Dt:
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01/16/2007
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Application #:
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10159849
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Filing Dt:
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05/31/2002
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Publication #:
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Pub Dt:
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12/05/2002
| | | | |
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Title:
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TEST DEVICE FOR DYNAMIC MEMORY MODULES
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Patent #:
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Issue Dt:
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10/21/2003
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Application #:
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10159858
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Filing Dt:
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05/31/2002
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Publication #:
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Pub Dt:
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12/05/2002
| | | | |
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Title:
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MEMORY MODULE, METHOD FOR ACTIVATING A MEMORY CELL, AND METHOD FOR REPAIRING A DEFECTIVE MEMORY CELL
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Patent #:
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Issue Dt:
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06/15/2004
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Application #:
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10159861
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Filing Dt:
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05/31/2002
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Publication #:
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Pub Dt:
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03/13/2003
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Title:
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MATERIAL AND ADDITIVE FOR HIGHLY CROSSLINKED CHEMICALLY AND THERMALLY STABLE POLYHYDROXYAMIDE POLYMERS
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Patent #:
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Issue Dt:
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08/24/2004
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Application #:
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10160446
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Filing Dt:
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05/30/2002
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Publication #:
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Pub Dt:
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02/13/2003
| | | | |
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Title:
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PRINTED CIRCUIT BOARD FOR SEMICONDUCTOR MEMORY DEVICE
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Patent #:
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Issue Dt:
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06/07/2005
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Application #:
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10163054
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Filing Dt:
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06/05/2002
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Publication #:
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Pub Dt:
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12/05/2002
| | | | |
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Title:
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METHOD FOR CARRYING OUT A RULE-BASED OPTICAL PROXIMITY CORRECTION WITH SIMULTANEOUS SCATTER BAR INSERTION
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Patent #:
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Issue Dt:
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01/06/2004
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Application #:
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10164213
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Filing Dt:
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06/06/2002
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Publication #:
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Pub Dt:
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12/26/2002
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Title:
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METHOD FOR RECOGNIZING AND REPLACING DEFECTIVE MEMORY CELLS IN A MEMORY
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Patent #:
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Issue Dt:
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03/30/2004
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Application #:
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10164453
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Filing Dt:
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06/06/2002
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Publication #:
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Pub Dt:
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01/16/2003
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Title:
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METHOD FOR COMBINING LOGIC-BASED CIRCUIT UNITS AND MEMORY-BASED CIRCUIT UNITS AND CIRCUIT ARRANGEMENT
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Patent #:
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Issue Dt:
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02/13/2007
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Application #:
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10164770
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Filing Dt:
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06/07/2002
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Publication #:
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Pub Dt:
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02/13/2003
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Title:
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DEVICE FOR AND METHOD OF EXAMINING THE SIGNAL PERFORMANCE OF SEMICONDUCTOR CIRCUITS
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Patent #:
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Issue Dt:
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07/08/2003
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Application #:
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10166813
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Filing Dt:
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06/11/2002
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Publication #:
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Pub Dt:
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02/06/2003
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Title:
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ONE-TRANSISTOR MEMORY CELL CONFIGURATION AND METHOD FOR ITS FABRICATION
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Patent #:
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Issue Dt:
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11/25/2003
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Application #:
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10166981
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Filing Dt:
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06/11/2002
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Publication #:
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Pub Dt:
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02/06/2003
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Title:
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OUTPUT DRIVERS FOR IC
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Patent #:
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Issue Dt:
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10/19/2004
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Application #:
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10167785
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Filing Dt:
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06/12/2002
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Publication #:
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Pub Dt:
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12/12/2002
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Title:
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METHOD FOR PRODUCING AND/OR RENEWING AN ETCHING MASK
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Patent #:
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Issue Dt:
|
11/11/2003
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Application #:
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10170290
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Filing Dt:
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06/13/2002
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Publication #:
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Pub Dt:
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12/19/2002
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Title:
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CIRCUIT CONFIGURATION WITH A PLURALITY OF TRANSISTORS OF TWO DIFFERENT CONDUCTIVITY TYPES
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Patent #:
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Issue Dt:
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11/21/2006
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Application #:
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10171098
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Filing Dt:
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06/13/2002
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Publication #:
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Pub Dt:
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01/16/2003
| | | | |
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Title:
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TRANSMITTING DATA INTO A MEMORY CELL ARRAY
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Patent #:
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Issue Dt:
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01/02/2007
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Application #:
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10173285
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Filing Dt:
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06/17/2002
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Publication #:
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Pub Dt:
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01/16/2003
| | | | |
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Title:
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APPARATUS AND METHOD FOR TESTING A DEVICE FOR STORING DATA
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Patent #:
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Issue Dt:
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01/20/2004
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Application #:
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10174646
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Filing Dt:
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06/18/2002
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Publication #:
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Pub Dt:
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12/19/2002
| | | | |
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Title:
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ALTERNATING PHASE MASK
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Patent #:
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Issue Dt:
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08/24/2004
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Application #:
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10175591
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Filing Dt:
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06/19/2002
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Publication #:
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Pub Dt:
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02/27/2003
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Title:
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METHOD FOR CONTROLLING THE QUALITY OF A LITHOGRAPHIC STRUCTURING STEP
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Patent #:
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Issue Dt:
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03/21/2006
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Application #:
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10178249
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Filing Dt:
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06/24/2002
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Publication #:
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Pub Dt:
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01/16/2003
| | | | |
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Title:
|
DELAY LOCKED LOOP
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Patent #:
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Issue Dt:
|
12/09/2003
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Application #:
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10178251
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Filing Dt:
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06/24/2002
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Publication #:
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Pub Dt:
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01/02/2003
| | | | |
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Title:
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DELAY LOCKED LOOP FOR GENERATING COMPLEMENTARY CLOCK SIGNALS
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Patent #:
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Issue Dt:
|
09/21/2004
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Application #:
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10178252
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Filing Dt:
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06/24/2002
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Publication #:
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Pub Dt:
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12/26/2002
| | | | |
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Title:
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METHOD AND SYSTEM FOR BIDIRECTIONAL SIGNAL TRANSMISSION
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Patent #:
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Issue Dt:
|
06/15/2004
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Application #:
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10178641
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Filing Dt:
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06/24/2002
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Publication #:
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Pub Dt:
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01/02/2003
| | | | |
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Title:
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METHOD OF FORMING A BITLINE AND A BITLINE CONTACT, AND DYNAMIC MEMORY CELL INCLUDING A BITLINE AND BITLINE MADE CONTACT ACCORDING TO THE METHOD
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Patent #:
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|
Issue Dt:
|
11/01/2005
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Application #:
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10179002
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Filing Dt:
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06/25/2002
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Publication #:
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Pub Dt:
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03/27/2003
| | | | |
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Title:
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MEMORY CHIP AND APPARATUS FOR TESTING A MEMORY CHIP
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Patent #:
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Issue Dt:
|
10/07/2003
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Application #:
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10179751
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Filing Dt:
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06/25/2002
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Publication #:
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Pub Dt:
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01/09/2003
| | | | |
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Title:
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LASER PROGRAMMING OF INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
|
02/22/2005
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Application #:
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10180440
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Filing Dt:
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06/26/2002
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Publication #:
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Pub Dt:
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12/26/2002
| | | | |
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Title:
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PROCESS AND DEVICE FOR THE ABRASIVE MACHINING OF SURFACES, IN PARTICULAR SEMICONDUCTOR WAFERS
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|
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Patent #:
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|
Issue Dt:
|
03/14/2006
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Application #:
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10180818
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Filing Dt:
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06/26/2002
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Publication #:
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Pub Dt:
|
01/02/2003
| | | | |
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Title:
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DEVICE FOR DRIVING A MEMORY CELL OF A MEMORY MODULE BY MEANS OF A CHARGE STORE
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Patent #:
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|
Issue Dt:
|
12/28/2004
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Application #:
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10184127
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Filing Dt:
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06/28/2002
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Publication #:
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Pub Dt:
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01/01/2004
| | | | |
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Title:
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HARDMASK OF AMORPHOUS CARBON-HYDROGEN (A-C:H) LAYERS WITH TUNABLE ETCH RESISTIVITY
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|
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Patent #:
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|
Issue Dt:
|
12/16/2003
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Application #:
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10185245
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Filing Dt:
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06/27/2002
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Publication #:
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Pub Dt:
|
01/16/2003
| | | | |
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Title:
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MODULE UNIT FOR MEMORY MODULES AND METHOD FOR ITS PRODUCTION
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Patent #:
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|
Issue Dt:
|
11/04/2003
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Application #:
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10185280
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Filing Dt:
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06/27/2002
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Publication #:
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Pub Dt:
|
01/02/2003
| | | | |
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Title:
|
RAM CIRCUIT WITH REDUNDANT WORD LINES
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|
|
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Patent #:
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|
Issue Dt:
|
01/11/2005
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Application #:
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10185281
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Filing Dt:
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06/27/2002
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|
Publication #:
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Pub Dt:
|
01/02/2003
| | | | |
|
Title:
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METHOD FOR PRODUCING A PHASE SHIFT MASK
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|
|
|
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Patent #:
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|
Issue Dt:
|
04/13/2004
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Application #:
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10185628
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Filing Dt:
|
06/28/2002
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|
Publication #:
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Pub Dt:
|
01/02/2003
| | | | |
|
Title:
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INTEGRATED DYNAMIC MEMORY AND METHOD FOR OPERATING IT
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|
|
|
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Patent #:
|
|
Issue Dt:
|
03/08/2005
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Application #:
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10185631
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Filing Dt:
|
06/28/2002
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|
Publication #:
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Pub Dt:
|
01/02/2003
| | | | |
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Title:
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METHOD OF PRODUCING LARGE-AREA MEMBRANE MASKS BY DRY ETCHING
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|
|
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Patent #:
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|
Issue Dt:
|
08/12/2003
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Application #:
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10186043
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Filing Dt:
|
06/28/2002
|
|
Title:
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METHOD OF MANUFACTURING CIRCUIT WITH BURIED STRAP INCLUDING A LINER
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|
|
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Patent #:
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|
Issue Dt:
|
06/29/2004
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Application #:
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10186113
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Filing Dt:
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06/28/2002
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Publication #:
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Pub Dt:
|
01/02/2003
| | | | |
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Title:
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EXPOSURE MASK WITH REPAIRED DUMMY STRUCTURE AND METHOD OF REPAIRING AN EXPOSURE MASK
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|
|
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Patent #:
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|
Issue Dt:
|
03/21/2006
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Application #:
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10186138
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Filing Dt:
|
06/28/2002
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|
Publication #:
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Pub Dt:
|
01/16/2003
| | | | |
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Title:
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METHOD AND BUS SYSTEM FOR SYNCHRONIZING A DATA EXCHANGE BETWEEN A DATA SOURCE AND A CONTROL DEVICE
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|
|
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Patent #:
|
|
Issue Dt:
|
07/06/2004
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Application #:
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10186139
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Filing Dt:
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06/28/2002
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Publication #:
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Pub Dt:
|
04/17/2003
| | | | |
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Title:
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AMPLIFICATION OF RESIST STRUCTURES OF FLUORINATED RESIST POLYMERS BY STRUCTURAL GROWTH OF THE STRUCTURES BY TARGETED CHEMICAL BONDING OF FLUORINATED OLIGOMERS
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Patent #:
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|
Issue Dt:
|
11/30/2004
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Application #:
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10186327
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Filing Dt:
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06/28/2002
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Publication #:
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Pub Dt:
|
03/13/2003
| | | | |
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Title:
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ON CHIP SCRAMBLING
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Patent #:
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Issue Dt:
|
06/29/2004
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Application #:
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10186596
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Filing Dt:
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07/01/2002
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Publication #:
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Pub Dt:
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01/23/2003
| | | | |
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Title:
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DEVICE AND METHOD FOR CALIBRATING THE PULSE DURATION OF A SIGNAL SOURCE
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Patent #:
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|
Issue Dt:
|
02/22/2005
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Application #:
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10186597
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Filing Dt:
|
07/01/2002
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Publication #:
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Pub Dt:
|
07/10/2003
| | | | |
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Title:
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METHOD FOR FABRICATING A SEMICONDUCTOR MEMORY DEVICE
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Patent #:
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Issue Dt:
|
07/29/2003
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Application #:
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10186599
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Filing Dt:
|
07/01/2002
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Publication #:
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Pub Dt:
|
01/02/2003
| | | | |
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Title:
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CIRCUIT CONFIGURATION AND METHOD FOR DETERMINING A TIME CONSTANT OF A STORAGE CAPACITOR OF A MEMORY CELL IN A SEMICONDUCTOR MEMORY
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|
|
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Patent #:
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|
Issue Dt:
|
11/16/2004
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Application #:
|
10186607
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Filing Dt:
|
07/01/2002
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Publication #:
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Pub Dt:
|
03/27/2003
| | | | |
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Title:
|
METHOD FOR FABRICATING A SEMICONDUCTOR MEMORY DEVICE
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|
|
|
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Patent #:
|
|
Issue Dt:
|
04/19/2005
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Application #:
|
10186644
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Filing Dt:
|
07/01/2002
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|
Publication #:
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Pub Dt:
|
01/30/2003
| | | | |
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Title:
|
ELECTRONIC COMPONENT, TESTER DEVICE AND METHOD FOR CALIBRATING A TESTER DEVICE
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|
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Patent #:
|
|
Issue Dt:
|
03/09/2004
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Application #:
|
10186645
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Filing Dt:
|
07/01/2002
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|
Publication #:
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Pub Dt:
|
03/20/2003
| | | | |
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Title:
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FERAM MEMORY AND METHOD FOR MANUFACTURING IT
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|
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Patent #:
|
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Issue Dt:
|
09/20/2005
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Application #:
|
10186648
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Filing Dt:
|
07/01/2002
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|
Publication #:
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Pub Dt:
|
04/17/2003
| | | | |
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Title:
|
NEGATIVE RESIST PROCESS WITH SIMULTANEOUS DEVELOPMENT AND AROMATIZATION OF RESIST STRUCTURES
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|
|
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Patent #:
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|
Issue Dt:
|
10/21/2003
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Application #:
|
10186650
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Filing Dt:
|
07/01/2002
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|
Publication #:
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Pub Dt:
|
01/02/2003
| | | | |
|
Title:
|
METHOD AND INPUT CIRCUIT FOR EVALUATING A DATA SIGNAL AT AN INPUT OF A MEMORY COMPONENT
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|
|
|
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Patent #:
|
|
Issue Dt:
|
06/27/2006
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Application #:
|
10186651
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Filing Dt:
|
07/01/2002
|
|
Publication #:
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Pub Dt:
|
04/10/2003
| | | | |
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Title:
|
CHEMICAL CONSOLIDATION OF PHOTORESISTS IN THE UV RANGE
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|
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Patent #:
|
|
Issue Dt:
|
02/14/2006
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Application #:
|
10186652
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Filing Dt:
|
07/01/2002
|
|
Publication #:
|
|
Pub Dt:
|
04/03/2003
| | | | |
|
Title:
|
NEGATIVE RESIST PROCESS WITH SIMULTANEOUS DEVELOPMENT AND CHEMICAL CONSOLIDATION OF RESIST STRUCTURES
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|
|
|
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Patent #:
|
|
Issue Dt:
|
06/17/2003
|
Application #:
|
10186656
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Filing Dt:
|
07/01/2002
|
|
Publication #:
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Pub Dt:
|
01/02/2003
| | | | |
|
Title:
|
METHOD AND INSTALLATION FOR FABRICATING ONE-SIDED BURIED STRAPS
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|
|
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|
Patent #:
|
|
Issue Dt:
|
04/25/2006
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Application #:
|
10186657
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Filing Dt:
|
07/01/2002
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|
Publication #:
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Pub Dt:
|
05/08/2003
| | | | |
|
Title:
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PHOTORESISTS WITH REACTION ANCHORS FOR CHEMICAL CONSOLIDATION OF RESIST STRUCTURES FOR EXPOSURES AT 157 NM
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|
|
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Patent #:
|
|
Issue Dt:
|
12/07/2004
|
Application #:
|
10186658
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Filing Dt:
|
07/01/2002
|
|
Publication #:
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|
Pub Dt:
|
02/06/2003
| | | | |
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Title:
|
METHOD OF PRODUCING ORGANIC SEMICONDUCTORS HAVING HIGH CHARGE CARRIER MOBILITY THROUGH PI-CONJUGATED CROSSLINKING GROUPS
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|
|
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Patent #:
|
|
Issue Dt:
|
08/03/2004
|
Application #:
|
10186660
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Filing Dt:
|
07/01/2002
|
|
Publication #:
|
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Pub Dt:
|
05/01/2003
| | | | |
|
Title:
|
NEGATIVE RESIST PROCESS WITH SIMULTANEOUS DEVELOPMENT AND SILYLATION
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/10/2004
|
Application #:
|
10186662
|
Filing Dt:
|
07/01/2002
|
|
Publication #:
|
|
Pub Dt:
|
03/27/2003
| | | | |
|
Title:
|
METHOD FOR FABRICATING A SEMICONDUCTOR MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/13/2004
|
Application #:
|
10186728
|
Filing Dt:
|
07/01/2002
|
|
Publication #:
|
|
Pub Dt:
|
01/02/2003
| | | | |
|
Title:
|
INTEGRATED CIRCUIT FOR RECEIVING A CLOCK SIGNAL, PARTICULARLY FOR A SEMICONDUCTOR MEMORY CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/30/2004
|
Application #:
|
10186971
|
Filing Dt:
|
07/01/2002
|
|
Publication #:
|
|
Pub Dt:
|
01/16/2003
| | | | |
|
Title:
|
PROCESS FOR THE ABRASIVE MACHINING OF SURFACES, IN PARTICULAR OF SEMICONDUCTOR WAFERS
|
|
