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Reel/Frame:023773/0457   Pages: 398
Recorded: 01/13/2010
Attorney Dkt #:609612800100
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 450
Page 5 of 5
Pages: 1 2 3 4 5
1
Patent #:
Issue Dt:
06/15/2004
Application #:
10310930
Filing Dt:
12/05/2002
Publication #:
Pub Dt:
06/05/2003
Title:
METHOD FOR DRIVING MEMORY CELLS OF A DYNAMIC SEMICONDUCTOR MEMORY AND CIRCUIT CONFIGURATION
2
Patent #:
Issue Dt:
05/31/2005
Application #:
10314049
Filing Dt:
12/04/2002
Publication #:
Pub Dt:
06/26/2003
Title:
LAYER ARRANGEMENT, MEMORY CELL, MEMORY CELL ARRANGEMENT AND METHOD FOR PRODUCING A LAYER ARRANGEMENT
3
Patent #:
Issue Dt:
04/19/2005
Application #:
10317972
Filing Dt:
12/12/2002
Publication #:
Pub Dt:
06/12/2003
Title:
METHOD FOR OPERATING A SEMICONDUCTOR MEMORY, AND SEMICONDUCTOR MEMORY
4
Patent #:
Issue Dt:
03/30/2004
Application #:
10320127
Filing Dt:
12/16/2002
Publication #:
Pub Dt:
06/19/2003
Title:
CONTACT PIN FOR TESTING MICROELECTRONIC COMPONENTS HAVING SUBSTANTIALLY SPHERICAL CONTACTS
5
Patent #:
Issue Dt:
08/24/2004
Application #:
10321185
Filing Dt:
12/17/2002
Publication #:
Pub Dt:
06/26/2003
Title:
METHOD FOR TRENCH ETCHING
6
Patent #:
Issue Dt:
08/31/2004
Application #:
10324432
Filing Dt:
12/20/2002
Publication #:
Pub Dt:
06/26/2003
Title:
INTEGRATED CIRCUIT HAVING A CONNECTION PAD FOR STIPULATING ONE OF A PLURALITY OF ORGANIZATION FORMS, AND METHOD FOR OPERATING THE CIRCUIT
7
Patent #:
Issue Dt:
11/01/2005
Application #:
10325100
Filing Dt:
12/20/2002
Publication #:
Pub Dt:
07/31/2003
Title:
METHOD FOR ACTIVATING FUSE UNITS IN ELECTRONIC CIRCUIT DEVICE
8
Patent #:
Issue Dt:
03/06/2007
Application #:
10325250
Filing Dt:
12/19/2002
Publication #:
Pub Dt:
07/10/2003
Title:
MEMORY UNIT AND BRANCHED COMMAND/ADDRESS BUS ARCHITECTURE BETWEEN A MEMORY REGISTER AND A PLURALITY OF MEMORY UNITS
9
Patent #:
Issue Dt:
08/23/2005
Application #:
10325251
Filing Dt:
12/19/2002
Publication #:
Pub Dt:
06/19/2003
Title:
ELECTRONIC DEVICE AND LEADFRAME AND METHODS FOR PRODUCING THE ELECTRONIC DEVICE AND THE LEADFRAME
10
Patent #:
Issue Dt:
04/20/2004
Application #:
10325349
Filing Dt:
12/18/2002
Publication #:
Pub Dt:
06/19/2003
Title:
INTEGRATED MEMORY HAVING A PRECHARGE CIRCUIT FOR PRECHARGING A BIT LINE
11
Patent #:
Issue Dt:
09/28/2004
Application #:
10330444
Filing Dt:
12/27/2002
Publication #:
Pub Dt:
07/03/2003
Title:
PROCESS FACILITY HAVING AT LEAST TWO PHYSICAL UNITS EACH HAVING A REDUCED DENSITY OF CONTAMINATING PARTICLES WITH RESPECT TO THE SURROUNDINGS
12
Patent #:
Issue Dt:
03/14/2006
Application #:
10331641
Filing Dt:
12/30/2002
Publication #:
Pub Dt:
07/31/2003
Title:
PHOTOMASK AND METHOD OF STRUCTURING A PHOTORESIST BY DOUBLE EXPOSURE WITH IMAGING AUXILIARY STRUCTURES AND DIFFERENT EXPOSURE TOOLS
13
Patent #:
Issue Dt:
11/16/2004
Application #:
10339031
Filing Dt:
01/09/2003
Publication #:
Pub Dt:
08/28/2003
Title:
METHOD FOR STORING DATA IN A MEMORY DEVICE WITH THE POSSIBILITY OF ACCESS TO REDUNDANT MEMORY CELLS
14
Patent #:
Issue Dt:
10/19/2004
Application #:
10340046
Filing Dt:
01/10/2003
Publication #:
Pub Dt:
07/10/2003
Title:
METHOD AND LOGIC/MEMORY MODULE FOR CORRECTING THE DUTY CYCLE OF AT LEAST ONE CONTROL/REFERENCE SIGNAL
15
Patent #:
Issue Dt:
09/19/2006
Application #:
10340047
Filing Dt:
01/10/2003
Publication #:
Pub Dt:
07/10/2003
Title:
METHOD FOR PROCESSING A SUBSTRATE TO FORM A STRUCTURE
16
Patent #:
Issue Dt:
01/11/2005
Application #:
10340464
Filing Dt:
01/10/2003
Publication #:
Pub Dt:
07/10/2003
Title:
CONTACT BASE WITH DETACHABLE CONTACTS FOR MAKING ELECTRICAL CONTACT WITH AN ELECTRONIC COMPONENT, IN PARTICULAR A MULTIPIN ELECTRONIC COMPONENT, AND MODULE CARRIER
17
Patent #:
Issue Dt:
01/09/2007
Application #:
10340987
Filing Dt:
01/13/2003
Publication #:
Pub Dt:
07/17/2003
Title:
RESIST FOR FORMING A STRUCTURE FOR ALIGNING AN ELECTRON OR ION BEAM AND TECHNIQUE FOR FORMING THE STRUCTURE
18
Patent #:
Issue Dt:
06/20/2006
Application #:
10342901
Filing Dt:
01/15/2003
Publication #:
Pub Dt:
05/06/2004
Title:
DIGITAL MEMORY CIRCUIT HAVING A PLURALITY OF MEMORY BANKS
19
Patent #:
Issue Dt:
03/14/2006
Application #:
10348148
Filing Dt:
01/21/2003
Publication #:
Pub Dt:
02/19/2004
Title:
MEMORY CELL HAVING A THIN INSULATION COLLAR AND MEMORY MODULE
20
Patent #:
Issue Dt:
11/23/2004
Application #:
10348150
Filing Dt:
01/21/2003
Publication #:
Pub Dt:
07/24/2003
Title:
METHOD FOR PRODUCING A CAVITY IN A MONOCRYSTALLINE SILICON SUBSTRATE AND A SEMICONDUCTOR COMPONENT HAVING A CAVITY IN A MONOCRYSTALLINE SILICON SUBSTRATE WITH AN EPITAXIAL COVERING LAYER
21
Patent #:
Issue Dt:
07/18/2006
Application #:
10353463
Filing Dt:
01/29/2003
Publication #:
Pub Dt:
08/14/2003
Title:
PHOTOLITHOGRAPHIC MASK
22
Patent #:
Issue Dt:
05/31/2005
Application #:
10353733
Filing Dt:
01/29/2003
Publication #:
Pub Dt:
01/20/2005
Title:
CHEMICAL MECHANICAL POLISHING (CMP) PROCESS USING FIXED ABRASIVE PADS
23
Patent #:
Issue Dt:
12/28/2004
Application #:
10356921
Filing Dt:
01/30/2003
Publication #:
Pub Dt:
09/11/2003
Title:
METHOD OF CHECKING ELECTRICAL CONNECTIONS BETWEEN A MEMORY MODULE AND A SEMICONDUCTOR MEMORY CHIP
24
Patent #:
Issue Dt:
12/30/2003
Application #:
10360456
Filing Dt:
02/06/2003
Publication #:
Pub Dt:
08/07/2003
Title:
MEMORY MODULE WITH IMPROVED ELECTRICAL PROPERTIES
25
Patent #:
Issue Dt:
09/07/2004
Application #:
10364014
Filing Dt:
02/10/2003
Publication #:
Pub Dt:
08/21/2003
Title:
ADDRESSING DEVICE FOR SELECTING REGULAR AND REDUNDANT ELEMENTS
26
Patent #:
Issue Dt:
11/23/2004
Application #:
10368081
Filing Dt:
02/18/2003
Publication #:
Pub Dt:
08/21/2003
Title:
INTEGRATED MEMORY AND METHOD FOR OPERATING AN INTEGRATED MEMORY
27
Patent #:
Issue Dt:
03/22/2005
Application #:
10368330
Filing Dt:
02/18/2003
Publication #:
Pub Dt:
08/21/2003
Title:
METHOD FOR GENERATING TEST SIGNALS FOR AN INTEGRATED CIRCUIT AND TEST LOGIC UNIT
28
Patent #:
Issue Dt:
02/28/2006
Application #:
10370857
Filing Dt:
02/20/2003
Publication #:
Pub Dt:
08/21/2003
Title:
METHOD FOR FORMING A HARD MASK IN A LAYER ON A PLANAR DEVICE
29
Patent #:
Issue Dt:
09/13/2005
Application #:
10372989
Filing Dt:
02/24/2003
Publication #:
Pub Dt:
07/07/2005
Title:
METHOD FOR FABRICATING A P-CHANNEL FIELD-EFFECT TRANSISTOR ON A SEMICONDUCTOR SUBSTRATE
30
Patent #:
Issue Dt:
03/29/2005
Application #:
10396841
Filing Dt:
03/25/2003
Publication #:
Pub Dt:
11/27/2003
Title:
ELECTRONIC COMPONENT WITH A SEMICONDUCTOR CHIP, METHOD OF PRODUCING AN ELECTRONIC COMPONENT AND A PANEL WITH A PLURALITY OF ELECTRONIC COMPONENTS
31
Patent #:
Issue Dt:
10/11/2005
Application #:
10408806
Filing Dt:
04/07/2003
Publication #:
Pub Dt:
12/11/2003
Title:
METHOD FOR COMPENSATING FOR SCATTER/REFLECTION EFFECTS IN PARTICLE BEAM LITHOGRAPHY
32
Patent #:
Issue Dt:
10/02/2007
Application #:
10422580
Filing Dt:
04/24/2003
Publication #:
Pub Dt:
10/30/2003
Title:
METHOD FOR NUMERICALLY SIMULATING AN ELECTRICAL CIRCUIT
33
Patent #:
Issue Dt:
01/11/2005
Application #:
10431900
Filing Dt:
05/08/2003
Publication #:
Pub Dt:
11/13/2003
Title:
METHOD FOR TESTING AN ELECTRONIC COMPONENT; COMPUTER PROGRAM PRODUCT, COMPUTER READABLE MEDIUM, AND COMPUTER EMBODYING THE METHOD; AND METHOD FOR DOWNLOADING THE PROGRAM EMBODYING THE METHOD
34
Patent #:
Issue Dt:
02/27/2007
Application #:
10439193
Filing Dt:
05/15/2003
Publication #:
Pub Dt:
12/18/2003
Title:
METHOD FOR PRODUCING A MASK SET FOR LITHOGRAPHY INCLUDING AT LEAST ONE MASK AND METHODS FOR IMAGING STRUCTURES OF A PREDETERMINED LAYOUT INTO A COMMON EXPOSURE PLANE
35
Patent #:
Issue Dt:
04/26/2005
Application #:
10447065
Filing Dt:
05/28/2003
Publication #:
Pub Dt:
12/02/2004
Title:
VERTICAL 8F2 CELL DRAM WITH ACTIVE AREA SELF-ALIGNED TO BIT LINE
36
Patent #:
Issue Dt:
12/27/2005
Application #:
10455764
Filing Dt:
06/05/2003
Publication #:
Pub Dt:
12/11/2003
Title:
METHOD FOR ELIMINATING PHASE CONFLICT CENTERS IN ALTERNATING PHASE MASKS, AND METHOD FOR PRODUCING ALTERNATING PHASE MASKS
37
Patent #:
Issue Dt:
02/28/2006
Application #:
10465103
Filing Dt:
06/19/2003
Publication #:
Pub Dt:
01/22/2004
Title:
METHOD FOR STRUCTURING A LITHOGRAPHY MASK
38
Patent #:
Issue Dt:
02/14/2006
Application #:
10600750
Filing Dt:
06/19/2003
Publication #:
Pub Dt:
05/12/2005
Title:
CIRCUIT ELEMENT HAVING A FIRST LAYER COMPOSED OF AN ELECTRICALLY INSULATING SUBSTRATE MATERIAL, A METHOD FOR PRODUCING A CIRCUIT ELEMENT, BISPYRIDINIUM COMPOUNDS AND THEIR USE IN CIRCUIT ELEMENTS
39
Patent #:
Issue Dt:
11/30/2004
Application #:
10606069
Filing Dt:
06/25/2003
Publication #:
Pub Dt:
02/19/2004
Title:
METHOD FOR FABRICATING MICROSTRUCTURES AND ARRANGEMENT OF MICROSTRUCTURES
40
Patent #:
Issue Dt:
09/28/2004
Application #:
10607033
Filing Dt:
06/26/2003
Publication #:
Pub Dt:
03/11/2004
Title:
METHOD FOR MANUFACTURING A BURIED STRAP CONTACT IN A MEMORY CELL
41
Patent #:
Issue Dt:
04/25/2006
Application #:
10615567
Filing Dt:
07/08/2003
Publication #:
Pub Dt:
01/08/2004
Title:
VERTICAL TRANSISTOR, AND A METHOD FOR PRODUCING A VERTICAL TRANSISTOR
42
Patent #:
Issue Dt:
01/09/2007
Application #:
10618056
Filing Dt:
07/11/2003
Publication #:
Pub Dt:
03/18/2004
Title:
APPARATUS AND METHOD FOR CALIBRATING SIGNALS
43
Patent #:
Issue Dt:
01/04/2005
Application #:
10626956
Filing Dt:
07/25/2003
Publication #:
Pub Dt:
02/05/2004
Title:
METHOD FOR FABRICATING A VERTICAL TRANSISTOR, AND SEMICONDUCTOR MEMORY CELL HAVING A TRENCH CAPACITOR AND AN ASSOCIATED VERTICAL SELECTION TRANSISTOR
44
Patent #:
Issue Dt:
07/26/2005
Application #:
10682649
Filing Dt:
10/09/2003
Publication #:
Pub Dt:
04/15/2004
Title:
MEMORY MODULE WITH A HEAT DISSIPATION MEANS
45
Patent #:
Issue Dt:
05/30/2006
Application #:
10690001
Filing Dt:
10/21/2003
Publication #:
Pub Dt:
05/06/2004
Title:
MULTI-LEVEL DRIVER STAGE
46
Patent #:
Issue Dt:
03/21/2006
Application #:
10733043
Filing Dt:
12/11/2003
Publication #:
Pub Dt:
07/15/2004
Title:
DYNAMIC MEMORY CELL AND METHOD OF MANUFACTURING SAME
47
Patent #:
Issue Dt:
07/11/2006
Application #:
10736775
Filing Dt:
12/17/2003
Publication #:
Pub Dt:
10/07/2004
Title:
METHOD FOR FABRICATING A PHOTOMASK FOR AN INTEGRATED CIRCUIT AND CORRESPONDING PHOTOMASK
48
Patent #:
Issue Dt:
10/16/2007
Application #:
10857635
Filing Dt:
05/28/2004
Publication #:
Pub Dt:
01/27/2005
Title:
CIRCUIT ELEMENT HAVING A FIRST LAYER OF AN ELECTRICALLY INSULATING SUBSTRATE MATERIAL AND METHOD FOR MANUFACTURING A CIRCUIT ELEMENT
49
Patent #:
Issue Dt:
08/02/2005
Application #:
10893561
Filing Dt:
07/16/2004
Publication #:
Pub Dt:
04/14/2005
Title:
METHOD FOR PRODUCING AN ELECTRICALLY CONDUCTIVE CONTACT
50
Patent #:
Issue Dt:
05/13/2003
Application #:
29155827
Filing Dt:
02/19/2002
Title:
MULTIMEDIA CHIP CARD
Assignor
1
Exec Dt:
04/25/2006
Assignee
1
GUSTAV-HEINEMANN-RING 212
MUNICH, GERMANY 81739
Correspondence name and address
BARRY E. BRETSCHNEIDER
C/O MORRISON AND FOERSTER LLP
1650 TYSONS BLVD. SUITE 400
MCLEAN, VA 22102

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