Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
|
| Reel/Frame: | 023774/0001 | |
| Pages: | 386 |
| | Recorded: | 01/13/2010 | | |
| Attorney Dkt #: | 609612800100 |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
|
|
Total properties:
9
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/23/2002
|
Application #:
|
09439254
|
Filing Dt:
|
11/12/1999
|
|
Title:
|
UNIVERSAL MEMORY CONTROLLER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/10/2001
|
Application #:
|
09439276
|
Filing Dt:
|
11/12/1999
|
|
Title:
|
METHODS AND APPARATUS FOR DETECTING THE COLLISION OF DATA ON A DATA BUS IN CASE OF OUT-OF-ORDER MEMORY ACCESSES OF DIFFERENT TIMES OF MEMORY ACCESS EXECUTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/11/2003
|
Application #:
|
09439544
|
Filing Dt:
|
11/12/1999
|
|
Title:
|
UNIVERSAL RESOURCE ACCESS CONTROLLER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/04/2001
|
Application #:
|
09439715
|
Filing Dt:
|
11/12/1999
|
|
Title:
|
METHOD OF SPEEDING UP ACCESS TO A MEMORY PAGE USING A NUMBER OF M PAGE TAG REGISTERS TO TRACK A STATE OF PHYSICAL PAGES IN A MEMORY DEVICE HAVING N MEMORY BANKS WHERE N IS GREATER THAN M
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2003
|
Application #:
|
09439867
|
Filing Dt:
|
11/12/1999
|
|
Title:
|
METHODS AND APPARATUS FOR PREDICTION OF THE TIME BETWEEN TWO CONSECUTIVE MEMORY ACCESSES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/01/2003
|
Application #:
|
09712993
|
Filing Dt:
|
11/14/2000
|
|
Title:
|
APPARATUS FOR DETECTIND DATA COLLISION ON DATA BUS FOR OUT-OF-ORDER MEMORY ACCESSES WITH ACCESS EXECUTION TIME BASED IN PART ON CHARACTERIZATION DATA SPECIFIC TO MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/15/2004
|
Application #:
|
09787966
|
Filing Dt:
|
05/29/2001
|
|
Title:
|
INTEGRATED CIRCUIT COMPRISING VERTICAL TRANSISTORS, AND A METHOD FOR THE PRODUCTION THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/10/2002
|
Application #:
|
09806427
|
Filing Dt:
|
07/03/2001
|
|
Title:
|
DRAM CELL ARRANGEMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/08/2004
|
Application #:
|
10338798
|
Filing Dt:
|
01/07/2003
|
|
Title:
|
ENCAPSULATION OF FERROELECTRIC CAPACITORS
|
|
|
Assignee
|
|
|
|
|
| GUSTAV-HEINEMANN-RING 212 |
| MUNICH, GERMANY 81739 |
|
|
Correspondence name and address
|
| |
BARRY E. BRETSCHNEIDER
|
| |
C/O MORRISON & FOERSTER LLP
|
| |
1650 TYSONS BLVD. SUITE 400
|
| |
MCLEAN, VA 22102
|
Search Results as of:
05/08/2024 04:34 PM
If you have any comments or questions concerning the data displayed,
contact
PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified:
August 25, 2017 v.2.6
| 
