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NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:023791/0001   Pages: 387
Recorded: 01/14/2010
Attorney Dkt #:609612800100
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 56
1
Patent #:
6713797
Issue Dt:
03/30/2004
Application #:
09197984
Filing Dt:
11/23/1998
Title:
TEXTURED BI-BASED OXIDE CERAMIC FILMS
2
Patent #:
6204158
Issue Dt:
03/20/2001
Application #:
09216371
Filing Dt:
12/18/1998
Title:
REDUCED DIFFUSION OF A MOBILE SPECIE FROM A METAL OXIDE CERAMIC INTO THE SUBSTRATE
3
Patent #:
6127878
Issue Dt:
10/03/2000
Application #:
09225664
Filing Dt:
01/05/1999
Title:
DRIVER CIRCUIT WITH NEGATIVE LOWER POWER RAIL
4
Patent #:
6204187
Issue Dt:
03/20/2001
Application #:
09226434
Filing Dt:
01/06/1999
Title:
CONTACT AND DEEP TRENCH PATTERNING
5
Patent #:
6143599
Issue Dt:
11/07/2000
Application #:
09235621
Filing Dt:
01/22/1999
Title:
METHOD FOR MANUFACTURING MEMORY CELL WITH TRENCH CAPACITOR
6
Patent #:
6127866
Issue Dt:
10/03/2000
Application #:
09239487
Filing Dt:
01/28/1999
Title:
DELAY-LOCKED-LOOP (DLL) HAVING SYMMETRICAL RISING AND FALLING CLOCK EDGE TYPE DELAYS
7
Patent #:
6762447
Issue Dt:
07/13/2004
Application #:
09245269
Filing Dt:
02/05/1999
Title:
FIELD-SHIELD-TRENCH ISOLATION FOR GIGABIT DRAMS
8
Patent #:
6140208
Issue Dt:
10/31/2000
Application #:
09245958
Filing Dt:
02/05/1999
Title:
SHALLOW TRENCH ISOLATION (STI) WITH BILAYER OF OXIDE-NITRIDE FOR VLSI APPLICATIONS
9
Patent #:
6087820
Issue Dt:
07/11/2000
Application #:
09265252
Filing Dt:
03/09/1999
Title:
CURRENT SOURCE
10
Patent #:
6215349
Issue Dt:
04/10/2001
Application #:
09265253
Filing Dt:
03/09/1999
Title:
CAPACITIVE COUPLED DRIVER CIRCUIT
11
Patent #:
6184107
Issue Dt:
02/06/2001
Application #:
09271124
Filing Dt:
03/17/1999
Title:
CAPACITOR TRENCH-TOP DIELECTRIC FOR SELF-ALIGNED DEVICE ISOLATION
12
Patent #:
6211544
Issue Dt:
04/03/2001
Application #:
09272215
Filing Dt:
03/18/1999
Title:
MEMORY CELL LAYOUT FOR REDUCED INTERACTION BETWEEN STORAGE NODES AND TRANSISTORS
13
Patent #:
6229364
Issue Dt:
05/08/2001
Application #:
09274633
Filing Dt:
03/23/1999
Title:
FREQUENCY RANGE TRIMMING FOR A DELAY LINE
14
Patent #:
6204140
Issue Dt:
03/20/2001
Application #:
09275337
Filing Dt:
03/24/1999
Title:
DYNAMIC RANDOM ACCESS MEMORY
15
Patent #:
6330697
Issue Dt:
12/11/2001
Application #:
09294866
Filing Dt:
04/20/1999
Title:
APPARATUS AND METHOD FOR PERFORMING A DEFECT LEAKAGE SCREEN TEST FOR MEMORY DEVICES
16
Patent #:
6252443
Issue Dt:
06/26/2001
Application #:
09295157
Filing Dt:
04/20/1999
Title:
DELAY ELEMENT USING A DELAY LOCKED LOOP
17
Patent #:
6190971
Issue Dt:
02/20/2001
Application #:
09311471
Filing Dt:
05/13/1999
Title:
FORMATION OF 5F2 CELL WITH PARTIALLY VERTICAL TRANSISTOR AND GATE CONDUCTOR ALIGNED BURIED STRAP WITH RAISED SHALLOW TRENCH ISOLATION REGION
18
Patent #:
6225224
Issue Dt:
05/01/2001
Application #:
09315090
Filing Dt:
05/19/1999
Title:
SYSTEM FOR DISPENSING POLISHING LIQUID DURING CHEMICAL MECHANICAL POLISHING OF A SEMICONDUCTOR WAFER
19
Patent #:
6295998
Issue Dt:
10/02/2001
Application #:
09318155
Filing Dt:
05/25/1999
Title:
TEMPERATURE CONTROLLED GASSIFICATION OF DEIONIZED WATER FOR MEGASONIC CLEANING OF SEMICONDUCTOR WAFERS
20
Patent #:
6167891
Issue Dt:
01/02/2001
Application #:
09318156
Filing Dt:
05/25/1999
Title:
TEMPERATURE CONTROLLED DEGASSIFICATION OF DEIONIZED WATER FOR MEGASONIC CLEANING OF SEMICONDUCTOR WAFERS
21
Patent #:
6379577
Issue Dt:
04/30/2002
Application #:
09329894
Filing Dt:
06/10/1999
Publication #:
US20010037995
Pub Dt:
11/08/2001
Title:
HYDROGEN PEROXIDE AND ACID ETCHANT FOR A WET ETCH PROCESS
22
Patent #:
6081479
Issue Dt:
06/27/2000
Application #:
09333539
Filing Dt:
06/15/1999
Title:
HIERARCHICAL PREFETCH FOR SEMICONDUCTOR MEMORIES
23
Patent #:
6501131
Issue Dt:
12/31/2002
Application #:
09359291
Filing Dt:
07/22/1999
Title:
TRANSISTORS HAVING INDEPENDENTLY ADJUSTABLE PARAMETERS
24
Patent #:
6320215
Issue Dt:
11/20/2001
Application #:
09359292
Filing Dt:
07/22/1999
Title:
CRYSTAL-AXIS-ALIGNED VERTICAL SIDE WALL DEVICE
25
Patent #:
6288436
Issue Dt:
09/11/2001
Application #:
09361960
Filing Dt:
07/27/1999
Title:
MIXED FUSE TECHNOLOGIES
26
Patent #:
6153902
Issue Dt:
11/28/2000
Application #:
09374687
Filing Dt:
08/16/1999
Title:
VERTICAL DRAM CELL WITH WORDLINE SELF-ALIGNED TO STORAGE TRENCH
27
Patent #:
6107177
Issue Dt:
08/22/2000
Application #:
09382933
Filing Dt:
08/25/1999
Title:
SILYLATION METHOD FOR REDUCING CRITICAL DIMENSION LOSS AND RESIST LOSS
28
Patent #:
6281084
Issue Dt:
08/28/2001
Application #:
09386832
Filing Dt:
08/31/1999
Title:
DISPOSABLE SPACERS FOR IMPROVED ARRAY GAPFILL IN HIGH DENSITY DRAMS
29
Patent #:
6396160
Issue Dt:
05/28/2002
Application #:
09395420
Filing Dt:
09/14/1999
Title:
FILL STRATEGIES IN THE OPTICAL KERF
30
Patent #:
6136709
Issue Dt:
10/24/2000
Application #:
09413265
Filing Dt:
10/06/1999
Title:
IMPROVED METAL LINE DEPOSITION PROCESS
31
Patent #:
6207584
Issue Dt:
03/27/2001
Application #:
09478270
Filing Dt:
01/05/2000
Title:
HIGH DIELECTRIC CONSTANT MATERIAL DEPOSITION TO ACHIEVE HIGH CAPACITANCE
32
Patent #:
6214661
Issue Dt:
04/10/2001
Application #:
09489771
Filing Dt:
01/21/2000
Title:
Method to prevent oxygen Out-Diffusion from BSTO containing Micro-Electronic device
33
Patent #:
6359471
Issue Dt:
03/19/2002
Application #:
09491645
Filing Dt:
01/27/2000
Title:
Mixed swing voltage repeaters for high resistance or high capacitance signal lines and methods therefor
34
Patent #:
6261967
Issue Dt:
07/17/2001
Application #:
09501479
Filing Dt:
02/09/2000
Title:
Easy to remove hard mask layer for semiconductor device fabrication
35
Patent #:
6799290
Issue Dt:
09/28/2004
Application #:
09512756
Filing Dt:
02/25/2000
Title:
DATA PATH CALIBRATION AND TESTING MODE USING A DATA BUS FOR SEMICONDUCTOR MEMORIES
36
Patent #:
6365328
Issue Dt:
04/02/2002
Application #:
09522883
Filing Dt:
03/10/2000
Title:
SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD
37
Patent #:
6195300
Issue Dt:
02/27/2001
Application #:
09536185
Filing Dt:
03/24/2000
Title:
Cbr refresh control for the redundancy array
38
Patent #:
6264789
Issue Dt:
07/24/2001
Application #:
09562218
Filing Dt:
04/28/2000
Title:
System for dispensing polishing liquid during chemical mechanical polishing of a semiconductor wafer
39
Patent #:
6323535
Issue Dt:
11/27/2001
Application #:
09595764
Filing Dt:
06/16/2000
Title:
Electrical fuses employing reverse biasing to enhance programming
40
Patent #:
6396096
Issue Dt:
05/28/2002
Application #:
09597401
Filing Dt:
06/21/2000
Title:
DESIGN LAYOUT FOR A DENSE MEMORY CELL STRUCTURE
41
Patent #:
6555430
Issue Dt:
04/29/2003
Application #:
09723420
Filing Dt:
11/28/2000
Title:
PROCESS FLOW FOR CAPACITANCE ENHANCEMENT IN A DRAM TRENCH
42
Patent #:
6258659
Issue Dt:
07/10/2001
Application #:
09725412
Filing Dt:
11/29/2000
Title:
Embedded vertical dram cells and dual workfunction logic gates
43
Patent #:
6522171
Issue Dt:
02/18/2003
Application #:
09759011
Filing Dt:
01/11/2001
Publication #:
US20020089352
Pub Dt:
07/11/2002
Title:
METHOD OF REDUCING SUB-THRESHOLD LEAKAGE IN CIRCUITS DURING STANDBY MODE
44
Patent #:
6483764
Issue Dt:
11/19/2002
Application #:
09761045
Filing Dt:
01/16/2001
Publication #:
US20020136075
Pub Dt:
09/26/2002
Title:
DYNAMIC DRAM REFRESH RATE ADJUSTMENT BASED ON CELL LEAKAGE MONITORING
45
Patent #:
6426247
Issue Dt:
07/30/2002
Application #:
09764824
Filing Dt:
01/17/2001
Title:
LOW BITLINE CAPACITANCE STRUCTURE AND METHOD OF MAKING SAME
46
Patent #:
6437401
Issue Dt:
08/20/2002
Application #:
09824957
Filing Dt:
04/03/2001
Title:
STRUCTURE AND METHOD FOR IMPROVED ISOLATION IN TRENCH STORAGE CELLS
47
Patent #:
6485355
Issue Dt:
11/26/2002
Application #:
09887790
Filing Dt:
06/22/2001
Publication #:
US20020197937
Pub Dt:
12/26/2002
Title:
METHOD TO INCREASE REMOVAL RATE OF OXIDE USING FIXED-ABRASIVE
48
Patent #:
6541810
Issue Dt:
04/01/2003
Application #:
09896741
Filing Dt:
06/29/2001
Publication #:
US20030001200
Pub Dt:
01/02/2003
Title:
MODIFIED VERTICAL MOSFET AND METHODS OF FORMATION THEREOF
49
Patent #:
6451662
Issue Dt:
09/17/2002
Application #:
09970635
Filing Dt:
10/04/2001
Title:
METHOD OF FORMING LOW-LEAKAGE ON-CHIP CAPACITOR
50
Patent #:
NONE
Issue Dt:
Application #:
10005861
Filing Dt:
11/08/2001
Publication #:
US20030087043
Pub Dt:
05/08/2003
Title:
Low k dielectric film deposition process
51
Patent #:
6570794
Issue Dt:
05/27/2003
Application #:
10034626
Filing Dt:
12/27/2001
Title:
TWISTED BIT-LINE COMPENSATION FOR DRAM HAVING REDUNDANCY
52
Patent #:
6576565
Issue Dt:
06/10/2003
Application #:
10075152
Filing Dt:
02/14/2002
Title:
RTCVD PROCESS AND REACTOR FOR IMPROVED CONFORMALITY AND STEP-COVERAGE
53
Patent #:
6667504
Issue Dt:
12/23/2003
Application #:
10249228
Filing Dt:
03/24/2003
Title:
SELF-ALIGNED BURIED STRAP PROCESS USING DOPED HDP OXIDE
54
Patent #:
6605838
Issue Dt:
08/12/2003
Application #:
10261219
Filing Dt:
09/30/2002
Title:
PROCESS FLOW FOR THICK ISOLATION COLLAR WITH REDUCED LENGTH
55
Patent #:
6778431
Issue Dt:
08/17/2004
Application #:
10318709
Filing Dt:
12/13/2002
Publication #:
US20040114439
Pub Dt:
06/17/2004
Title:
ARCHITECTURE FOR HIGH-SPEED MAGNETIC MEMORIES
56
Patent #:
6946345
Issue Dt:
09/20/2005
Application #:
10688612
Filing Dt:
10/17/2003
Publication #:
US20040188740
Pub Dt:
09/30/2004
Title:
SELF-ALIGNED BURIED STRAP PROCESS USING DOPED HDP OXIDE
Assignor
1
INFINEON TECHNOLOGIES NORTH AMERICA CORPORATION
Exec Dt:
04/25/2006
Assignee
1
QIMONDA AG
GUSTAV-HEINEMANN-RING 212
MUNICH, GERMANY 81739
Correspondence name and address
JONATHAN BOCKMAN
C/O MORRISON & FOERSTER LLP
1650 TYSONS BLVD. SUITE 400
MCLEAN, VA 22102

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