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Patent #:
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Issue Dt:
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03/23/2004
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Application #:
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08825311
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Filing Dt:
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03/28/1997
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Title:
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METHODS AND APPARATUS FOR INCREASING DATA BANDWIDTH INA DYNAMIC MEMORY DEVICE BY GENERATING A DELAYED ADDRESS TRANSITION DETECTION SIGNAL IN RESPONSE TO A COLUMN ADDRESS STROBE SIGNAL
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Patent #:
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Issue Dt:
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09/03/2002
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Application #:
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09597125
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Filing Dt:
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06/20/2000
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Title:
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CERIA SLURRY SOLUTION FOR IMPROVED DEFECT CONTROL OF SILICON DIOXIDE CHEMICAL-MECHANICAL POLISHING
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Patent #:
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Issue Dt:
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01/13/2004
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Application #:
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10032040
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Filing Dt:
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12/31/2001
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Publication #:
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Pub Dt:
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07/03/2003
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Title:
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HIGH ASPECT RATIO PBL SIN BARRIER FORMATION
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Patent #:
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Issue Dt:
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05/06/2003
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Application #:
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10032041
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Filing Dt:
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12/31/2001
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Title:
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ROUGH OXIDE HARD MASK FOR DT SURFACE AREA ENHANCEMENT FOR DT DRAM
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Patent #:
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Issue Dt:
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03/18/2003
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Application #:
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10062755
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Filing Dt:
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01/31/2002
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Publication #:
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Pub Dt:
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06/13/2002
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Title:
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FIELD EFFECT TRANSISTOR AND METHOD OF FABRICATION
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Patent #:
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Issue Dt:
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06/14/2005
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Application #:
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10065169
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Filing Dt:
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09/24/2002
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Publication #:
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Pub Dt:
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03/25/2004
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Title:
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HYBRID FUSES FOR REDUNDANCY
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Patent #:
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Issue Dt:
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01/11/2005
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Application #:
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10067587
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Filing Dt:
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02/04/2002
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Publication #:
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Pub Dt:
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08/07/2003
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Title:
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POLYELECTROLYTE DISPENSING POLISHING PAD, PRODUCTION THEREOF AND METHOD OF POLISHING A SUBSTRATE
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Patent #:
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Issue Dt:
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08/05/2003
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Application #:
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10068789
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Filing Dt:
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02/05/2002
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Publication #:
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Pub Dt:
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08/07/2003
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Title:
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DYNAMIC MEMORY REFRESH CIRCUITRY
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Patent #:
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Issue Dt:
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07/20/2004
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Application #:
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10094793
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Filing Dt:
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03/11/2002
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Publication #:
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Pub Dt:
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09/11/2003
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Title:
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DYNAMIC DELAY LINE CONTROL
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Patent #:
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Issue Dt:
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11/25/2003
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Application #:
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10095318
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Filing Dt:
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03/11/2002
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Publication #:
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Pub Dt:
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09/11/2003
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Title:
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METHOD AND APPARATUS FOR A DELAY LOCK LOOP
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Patent #:
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Issue Dt:
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08/17/2004
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Application #:
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10100639
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Filing Dt:
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03/19/2002
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Publication #:
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Pub Dt:
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09/25/2003
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Title:
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DELAY LOCK LOOP HAVING AN EDGE DETECTOR AND FIXED DELAY
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Patent #:
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Issue Dt:
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02/17/2004
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Application #:
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10100713
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Filing Dt:
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03/19/2002
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Publication #:
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Pub Dt:
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09/25/2003
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Title:
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DELAY LOCK LOOP HAVING A VARIABLE VOLTAGE REGULATOR
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Patent #:
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Issue Dt:
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04/25/2006
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Application #:
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10102145
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Filing Dt:
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03/20/2002
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Publication #:
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Pub Dt:
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09/25/2003
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Title:
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METHOD AND APPARATUS FOR PLACING AN INTEGRATED CIRCUIT INTO A DEFAULT MODE OF OPERATION
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Patent #:
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Issue Dt:
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11/21/2006
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Application #:
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10113386
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Filing Dt:
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03/29/2002
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Publication #:
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Pub Dt:
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10/02/2003
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Title:
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METHOD AND APPARATUS FOR PROVIDING ADJUSTABLE LATENCY FOR TEST MODE COMPRESSION
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Patent #:
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Issue Dt:
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07/01/2003
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Application #:
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10125118
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Filing Dt:
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04/18/2002
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Title:
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SPACER ASSISTED TRENCH TOP ISOLATION FOR VERTICAL DRAM'S
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Patent #:
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Issue Dt:
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06/01/2004
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Application #:
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10135144
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Filing Dt:
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04/30/2002
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Publication #:
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Pub Dt:
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03/04/2004
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Title:
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INTERNAL GENERATION OF REFERENCE VOLTAGE
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Patent #:
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Issue Dt:
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03/09/2004
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Application #:
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10138396
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Filing Dt:
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05/03/2002
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Publication #:
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Pub Dt:
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11/06/2003
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Title:
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LAYOUT FOR THERMALLY SELECTED CROSS-POINT MRAM CELL
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Patent #:
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Issue Dt:
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01/25/2005
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Application #:
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10143673
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Filing Dt:
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05/10/2002
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Publication #:
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Pub Dt:
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11/13/2003
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Title:
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METHOD OF FORMING SURFACE-SMOOTHING LAYER FOR SEMICONDUCTOR DEVICES WITH MAGNETIC MATERIAL LAYERS
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Patent #:
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Issue Dt:
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10/21/2003
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Application #:
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10146976
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Filing Dt:
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05/16/2002
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Title:
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METHOD OF MANUFACTURING MRAM OFFSET CELLS IN A DAMASCENE STRUCTURE
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Patent #:
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Issue Dt:
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09/16/2003
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Application #:
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10159169
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Filing Dt:
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05/31/2002
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Title:
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SUPPORT LINER FOR ISOLATION TRENCH HEIGHT CONTROL IN VERTICAL DRAM PROCESSING
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Patent #:
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Issue Dt:
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12/27/2005
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Application #:
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10161867
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Filing Dt:
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06/03/2002
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Publication #:
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Pub Dt:
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12/04/2003
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Title:
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LITHOGRAPHY ALIGNMENT AND OVERLAY MEASUREMENT MARKS FORMED BY RESIST MASK BLOCKING FOR MRAMS
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Patent #:
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Issue Dt:
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03/16/2004
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Application #:
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10165277
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Filing Dt:
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06/10/2002
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Publication #:
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Pub Dt:
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12/11/2003
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Title:
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SEMICONDUCTOR MEMORY DEVICE
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Patent #:
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Issue Dt:
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01/13/2004
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Application #:
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10178744
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Filing Dt:
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06/25/2002
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Publication #:
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Pub Dt:
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12/25/2003
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Title:
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SEMICONDUCTOR DEVICE HAVING FERROELECTRIC FILM AND MANUFACTURING METHOD THEREOF
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Patent #:
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Issue Dt:
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01/25/2005
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Application #:
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10210962
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Filing Dt:
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08/02/2002
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Publication #:
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Pub Dt:
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02/05/2004
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Title:
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METHOD AND APPARATUS FOR TEMPERATURE THROTTLING THE ACCESS FREQUENCY OF AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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01/06/2004
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Application #:
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10215747
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Filing Dt:
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08/09/2002
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Title:
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METHOD OF FORMING A GATE ELECTRODE CONTACT SPACER FOR A VERTICAL DRAM DEVICE
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Patent #:
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Issue Dt:
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04/06/2004
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Application #:
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10218449
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Filing Dt:
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08/13/2002
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Publication #:
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Pub Dt:
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02/19/2004
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Title:
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ATOMIC FORCE MICROSCOPY SCANNING METHODS
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Patent #:
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Issue Dt:
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01/30/2007
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Application #:
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10241032
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Filing Dt:
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09/11/2002
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Publication #:
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Pub Dt:
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03/11/2004
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Title:
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CIRCUIT AND METHOD FOR TESTING EMBEDDED DRAM CIRCUITS THROUGH DIRECT ACCESS MODE
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Patent #:
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Issue Dt:
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04/06/2004
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Application #:
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10248874
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Filing Dt:
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02/26/2003
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Publication #:
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Pub Dt:
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08/28/2003
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Title:
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CONTROL CIRCUIT FOR AN S-DRAM
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Patent #:
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Issue Dt:
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11/16/2004
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Application #:
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10249029
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Filing Dt:
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03/11/2003
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Publication #:
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Pub Dt:
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09/18/2003
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Title:
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LATENCY TIME CIRCUIT FOR AN S-DRAM
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Patent #:
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Issue Dt:
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06/22/2004
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Application #:
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10253148
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Filing Dt:
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09/24/2002
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Publication #:
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Pub Dt:
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03/25/2004
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Title:
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TOPOGRAPHY CORRECTION FOR TESTING OF REDUNDANT ARRAY ELEMENTS
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Patent #:
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Issue Dt:
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07/06/2004
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Application #:
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10254305
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Filing Dt:
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09/25/2002
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Publication #:
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Pub Dt:
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03/25/2004
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Title:
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DQS POSTAMBLE NOISE SUPPRESSION BY FORCING A MINIMUM PULSE LENGTH
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Patent #:
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Issue Dt:
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07/19/2005
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Application #:
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10254405
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Filing Dt:
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09/25/2002
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Publication #:
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Pub Dt:
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03/25/2004
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Title:
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PRODUCTION METHOD FOR A HALFTONE PHASE MASK
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Patent #:
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Issue Dt:
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12/23/2003
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Application #:
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10256181
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Filing Dt:
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09/26/2002
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Title:
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SEMICONDUCTOR MEMORY DEVICE AND TEST METHOD THEREOF USING ROW COMPRESSION TEST MODE
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Patent #:
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Issue Dt:
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05/11/2004
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Application #:
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10260229
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Filing Dt:
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09/27/2002
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Publication #:
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Pub Dt:
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04/01/2004
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Title:
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METHOD OF PATTERNING CAPACITORS AND CAPACITORS MADE THEREBY
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Patent #:
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Issue Dt:
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07/19/2005
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Application #:
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10265964
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Filing Dt:
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10/07/2002
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Publication #:
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Pub Dt:
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04/08/2004
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Title:
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BANK ADDRESS MAPPING ACCORDING TO BANK RETENTION TIME IN DYNAMIC RANDOM ACCESS MEMORIES
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Patent #:
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Issue Dt:
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07/06/2004
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Application #:
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10267262
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Filing Dt:
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10/09/2002
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Publication #:
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Pub Dt:
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04/22/2004
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Title:
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VOLTAGE REGULATOR WITH DISTRIBUTED OUTPUT TRANSISTOR
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Patent #:
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Issue Dt:
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06/07/2005
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Application #:
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10269005
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Filing Dt:
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10/10/2002
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Publication #:
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Pub Dt:
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04/15/2004
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Title:
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BIT LINE SEGMENTING IN RANDOM ACCESS MEMORIES
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Patent #:
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Issue Dt:
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07/06/2004
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Application #:
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10284995
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Filing Dt:
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10/31/2002
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Publication #:
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Pub Dt:
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05/06/2004
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Title:
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METHOD AND CIRCUIT FOR CONTROLLING FUSE BLOW
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Patent #:
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Issue Dt:
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04/25/2006
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Application #:
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10285027
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Filing Dt:
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10/31/2002
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Publication #:
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Pub Dt:
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05/06/2004
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Title:
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MEMORY DEVICE WITH COLUMN SELECT BEING VARIABLY DELAYED
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Patent #:
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Issue Dt:
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08/16/2005
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Application #:
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10289075
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Filing Dt:
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11/06/2002
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Publication #:
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Pub Dt:
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05/06/2004
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Title:
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USING ISOLATED P-WELL TRANSISTOR ARRANGEMENTS TO AVOID LEAKAGE CAUSED BY WORD LINE/BIT LINE SHORTS
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Patent #:
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Issue Dt:
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05/24/2005
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Application #:
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10291610
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Filing Dt:
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11/12/2002
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Publication #:
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Pub Dt:
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05/13/2004
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Title:
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SEMICONDUCTOR DEVICE HAVING SEMICONDUCTOR MEMORY WITH SENSE AMPLIFIER
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Patent #:
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Issue Dt:
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03/23/2004
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Application #:
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10299026
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Filing Dt:
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11/18/2002
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Title:
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METHOD AND IMPLEMENTATION OF AN ON-CHIP SELF REFRESH FEATURE
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Patent #:
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Issue Dt:
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04/20/2004
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Application #:
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10299037
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Filing Dt:
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11/18/2002
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Title:
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SOFT ERROR IMPROVEMENT FOR LATCHES
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Patent #:
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Issue Dt:
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04/08/2008
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Application #:
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10304506
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Filing Dt:
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11/26/2002
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Publication #:
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Pub Dt:
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05/27/2004
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Title:
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MODULAR TEST CONTROLLER WITH BISTCIRCUIT FOR TESTING EMBEDDED DRAM CIRCUITS
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Patent #:
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Issue Dt:
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08/31/2004
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Application #:
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10307230
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Filing Dt:
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11/29/2002
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Publication #:
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Pub Dt:
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06/03/2004
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Title:
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FERROELECTRIC CAPACITOR AND PROCESS FOR ITS MANUFACTURE
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Patent #:
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Issue Dt:
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09/20/2005
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Application #:
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10314797
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Filing Dt:
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12/09/2002
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Publication #:
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Pub Dt:
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10/02/2003
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Title:
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MEMORY CHIP, MEMORY COMPONENT AND CORRESPONDING MEMORY MODULE AND METHOD
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Patent #:
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Issue Dt:
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04/18/2006
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Application #:
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10315915
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Filing Dt:
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12/09/2002
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Publication #:
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Pub Dt:
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06/10/2004
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Title:
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FERROELECTRIC CAPACITOR AND PROCESS FOR ITS MANUFACTURE
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Patent #:
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Issue Dt:
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04/20/2004
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Application #:
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10320867
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Filing Dt:
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12/17/2002
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Title:
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SELF-ALIGNED CONTACT FORMATION USING DOUBLE SIN SPACERS
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Issue Dt:
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10/24/2006
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10322587
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12/19/2002
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Publication #:
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Pub Dt:
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06/24/2004
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Title:
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SEMICONDUCTOR DEVICE COMPRISING TRANSITION DETECTING CIRCUIT AND METHOD OF ACTIVATING THE SAME
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Patent #:
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Issue Dt:
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06/07/2005
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Application #:
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10350373
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Filing Dt:
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01/23/2003
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Publication #:
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Pub Dt:
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09/11/2003
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Title:
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METHOD OF IMPROVING THE QUALITY OF SOLDERED CONNECTIONS
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Issue Dt:
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05/16/2006
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Application #:
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10356314
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Filing Dt:
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01/31/2003
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Publication #:
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Pub Dt:
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08/05/2004
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Title:
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HARDMASK WITH HIGH SELECTIVITY FOR IR BARRIERS FOR FERROELECTIC CAPACITOR MANUFACTURING
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Patent #:
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Issue Dt:
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05/09/2006
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Application #:
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10356690
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Filing Dt:
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01/30/2003
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Publication #:
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Pub Dt:
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08/05/2004
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Title:
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SIDEWALL STRUCTURE AND METHOD OF FABRICATION FOR REDUCING OXYGEN DIFFUSION TO CONTACT PLUGS DURING CW HOLE REACTIVE ION ETCH PROCESSING
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Patent #:
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Issue Dt:
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06/07/2005
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Application #:
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10364070
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Filing Dt:
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02/11/2003
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Publication #:
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Pub Dt:
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09/18/2003
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Title:
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METHODS FOR FABRICATING A CONTACT FOR AN INTEGRATED CIRCUIT.
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Patent #:
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Issue Dt:
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07/27/2004
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Application #:
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10368333
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Filing Dt:
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02/18/2003
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Publication #:
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Pub Dt:
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08/21/2003
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Title:
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INTEGRATED DYNAMIC MEMORY WITH CONTROL CIRCUIT FOR CONTROLLING A REFRESH MODE OF MEMORY CELLS, AND METHOD FOR DRIVING THE MEMORY
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Patent #:
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Issue Dt:
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12/28/2004
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Application #:
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10375529
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Filing Dt:
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02/27/2003
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Publication #:
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Pub Dt:
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09/18/2003
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Title:
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METHOD AND DEVICE FOR DEPOSITING THIN LAYERS VIA ALD/CVD PROCESSES IN COMBINATION WITH RAPID THERMAL PROCESSES
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Patent #:
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Issue Dt:
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01/02/2007
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Application #:
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10375531
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Filing Dt:
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02/27/2003
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Publication #:
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Pub Dt:
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09/04/2003
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Title:
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LITHOGRAPHIC PROCESS FOR REDUCING THE LATERAL CHROMIUM STRUCTURE LOSS IN PHOTOMASK PRODUCTION USING CHEMICALLY AMPLIFIED RESISTS
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Patent #:
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Issue Dt:
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03/28/2006
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Application #:
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10375532
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Filing Dt:
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02/27/2003
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Publication #:
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Pub Dt:
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03/04/2004
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Title:
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PROCESS FOR INCREASING THE ETCH RESISTANCE AND FOR REDUCING THE HOLE AND TRENCH WIDTH OF A PHOTORESIST STRUCTURE USING SOLVENT SYSTEMS OF LOW POLARITY
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Patent #:
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Issue Dt:
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05/22/2007
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Application #:
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10376904
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Filing Dt:
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02/28/2003
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Publication #:
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Pub Dt:
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09/04/2003
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Title:
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RESIST FOR ELECTRON BEAM LITHOGRAPHY AND A PROCESS FOR PRODUCING PHOTOMASKS USING ELECTRON BEAM LITHOGRAPHY
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Patent #:
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Issue Dt:
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08/17/2004
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Application #:
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10377348
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Filing Dt:
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02/28/2003
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Publication #:
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Pub Dt:
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09/18/2003
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Title:
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METHOD AND MAGAZINE DEVICE FOR TESTING SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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09/07/2004
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Application #:
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10377349
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Filing Dt:
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02/28/2003
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Publication #:
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Pub Dt:
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08/28/2003
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Title:
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ADAPTER APPARATUS FOR MEMORY MODULES
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Patent #:
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Issue Dt:
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05/10/2005
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Application #:
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10377893
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Filing Dt:
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02/28/2003
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Publication #:
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Pub Dt:
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08/28/2003
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Title:
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POLYMER MATERIAL HAVING A LOW GLASS TRANSITION TEMPERATURE FOR USE IN CHEMICALLY AMPLIFIED PHOTORESISTS FOR SEMICONDUCTOR PRODUCTION
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Patent #:
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Issue Dt:
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02/20/2007
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Application #:
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10386147
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Filing Dt:
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03/11/2003
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Publication #:
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Pub Dt:
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01/08/2004
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Title:
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DIFFERENTAL CURRENT SOURCE FOR GENERATING DRAM REFRESH SIGNAL
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Patent #:
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Issue Dt:
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10/26/2004
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Application #:
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10386150
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Filing Dt:
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03/11/2003
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Publication #:
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Pub Dt:
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02/05/2004
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Title:
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LIMITER FOR REFRESH SIGNAL PERIOD IN DRAM
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Patent #:
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Issue Dt:
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10/26/2004
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Application #:
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10387993
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Filing Dt:
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03/13/2003
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Publication #:
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Pub Dt:
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09/16/2004
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Title:
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CIRCUIT TECHNIQUE FOR COLUMN REDUNDANCY FUSE LATCHES
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Patent #:
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Issue Dt:
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02/13/2007
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Application #:
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10389580
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Filing Dt:
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03/14/2003
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Publication #:
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Pub Dt:
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09/18/2003
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Title:
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TEST METHOD AND TEST APPARATUS FOR AN ELECTRONIC MODULE
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Patent #:
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Issue Dt:
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10/18/2005
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Application #:
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10389782
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Filing Dt:
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03/17/2003
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Publication #:
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Pub Dt:
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11/27/2003
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Title:
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INTEGRATED CIRCUIT AND METHOD FOR CONTROLLING A POWER SUPPLY THEREOF
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Patent #:
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Issue Dt:
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09/14/2004
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Application #:
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10390872
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Filing Dt:
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03/17/2003
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Publication #:
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Pub Dt:
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09/25/2003
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Title:
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METHOD FOR FABRICATING THIN METAL LAYERS FROM THE LIQUID PHASE
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Patent #:
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Issue Dt:
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07/20/2004
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Application #:
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10393525
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Filing Dt:
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03/20/2003
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Publication #:
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Pub Dt:
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02/12/2004
| | | | |
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Title:
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DUTY-CYCLE CORRECTION CIRCUIT
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Patent #:
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Issue Dt:
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10/03/2006
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Application #:
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10395455
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Filing Dt:
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03/24/2003
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Publication #:
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Pub Dt:
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12/25/2003
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Title:
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SEMICONDUCTOR CIRCUIT CONFIGURATION AND SEMICONDUCTOR MEMORY DEVICE
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Patent #:
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Issue Dt:
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09/07/2004
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Application #:
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10395457
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Filing Dt:
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03/24/2003
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Publication #:
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Pub Dt:
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09/25/2003
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Title:
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SEMICONDUCTOR MEMORY CELL AND SEMICONDUCTOR MEMORY DEVICE
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Patent #:
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Issue Dt:
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05/30/2006
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Application #:
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10401185
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Filing Dt:
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03/27/2003
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Publication #:
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Pub Dt:
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10/02/2003
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Title:
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INSTALLATION FOR PROCESSING A SEMICONDUCTOR WAFER AND METHOD FOR OPERATING THE INSTALLATION
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Patent #:
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Issue Dt:
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09/14/2004
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Application #:
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10401187
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Filing Dt:
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03/27/2003
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Publication #:
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Pub Dt:
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10/02/2003
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Title:
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ELECTRICAL COMPONENT WITH A CONTACT AND METHOD FOR FORMING A CONTACT ON A SEMICONDUCTOR MATERIAL
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Patent #:
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Issue Dt:
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07/12/2005
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Application #:
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10407714
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Filing Dt:
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04/04/2003
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Publication #:
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Pub Dt:
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10/09/2003
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Title:
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METHOD AND TEST STRUCTURE FOR DETERMINING RESISTANCES AT A PLURALITY OF INTERCONNECTED RESISTORS IN AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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05/16/2006
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Application #:
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10409012
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Filing Dt:
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04/08/2003
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Publication #:
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Pub Dt:
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10/09/2003
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Title:
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INTEGRATED MEMORY HAVING A MEMORY CELL ARRAY CONTAINING A PLURALITY OF MEMORY BANKS, AND CIRCUIT CONFIGURATION HAVING AN INTEGRATED MEMORY
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Patent #:
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Issue Dt:
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02/10/2004
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Application #:
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10410383
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Filing Dt:
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04/09/2003
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Publication #:
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Pub Dt:
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10/09/2003
| | | | |
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Title:
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CIRCUIT CONFIGURATION FOR CONVERTING LOGIC SIGNAL LEVELS
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Patent #:
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Issue Dt:
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04/13/2004
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Application #:
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10410933
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Filing Dt:
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04/10/2003
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Publication #:
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Pub Dt:
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10/23/2003
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Title:
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DRIVE CIRCUIT AND CONTROL METHOD
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Patent #:
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Issue Dt:
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03/15/2005
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Application #:
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10413505
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Filing Dt:
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04/14/2003
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Publication #:
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Pub Dt:
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12/11/2003
| | | | |
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Title:
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TARGETED DEPOSITION OF NANOTUBES
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Patent #:
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Issue Dt:
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02/13/2007
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Application #:
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10413812
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Filing Dt:
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04/15/2003
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Publication #:
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Pub Dt:
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12/04/2003
| | | | |
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Title:
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METHOD AND CONFIGURATION FOR REINFORCEMENT OF A DIELECTRIC LAYER AT DEFECTS BY SELF-ALIGNING AND SELF-LIMITING ELECTROCHEMICAL CONVERSION OF A SUBSTRATE MATERIAL
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Patent #:
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Issue Dt:
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08/24/2004
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Application #:
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10413814
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Filing Dt:
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04/15/2003
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Publication #:
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Pub Dt:
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10/16/2003
| | | | |
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Title:
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METHOD AND DEVICE FOR GENERATING A REFERENCE VOLTAGE
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Patent #:
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Issue Dt:
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09/14/2004
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Application #:
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10414836
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Filing Dt:
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04/16/2003
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Publication #:
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Pub Dt:
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10/16/2003
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Title:
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CIRCUIT CONFIGURATION WITH SIGNAL LINES FOR SERIALLY TRANSMITTING A PLURALITY OF BIT GROUPS
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Patent #:
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Issue Dt:
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08/10/2004
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Application #:
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10414837
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Filing Dt:
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04/16/2003
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Publication #:
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Pub Dt:
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10/16/2003
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Title:
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SEMICONDUCTOR ASSEMBLY WITH A SEMICONDUCTOR MODULE
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Patent #:
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Issue Dt:
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07/13/2004
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Application #:
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10417526
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Filing Dt:
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04/17/2003
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Title:
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PROCESS FOR FABRICATION OF A FERROCAPACITOR
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Patent #:
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Issue Dt:
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01/24/2006
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Application #:
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10419596
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Filing Dt:
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04/21/2003
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Publication #:
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Pub Dt:
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10/23/2003
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Title:
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SEMICONDUCTOR CIRCUIT AND INITIALIZATION METHOD
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Patent #:
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Issue Dt:
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06/19/2007
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Application #:
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10423812
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Filing Dt:
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04/25/2003
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Publication #:
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Pub Dt:
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11/20/2003
| | | | |
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Title:
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CIRCUIT CONFIGURATION AND METHOD FOR TRANSMITTING DIGITAL SIGNALS
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Patent #:
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Issue Dt:
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07/05/2005
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Application #:
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10424347
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Filing Dt:
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04/28/2003
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Publication #:
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Pub Dt:
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01/22/2004
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Title:
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SYSTEM AND METHOD FOR THE FUNCTIONAL TESTING OF SEMICONDUCTOR MEMORY CHIPS
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Patent #:
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Issue Dt:
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09/19/2006
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Application #:
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10424376
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Filing Dt:
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04/28/2003
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Publication #:
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Pub Dt:
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02/12/2004
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Title:
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METHODS FOR PRODUCING A DIELECTRIC, DIELECTRIC HAVING SELF-GENERATING PORES, MONOMER FOR POROUS DIELECTRICS, PROCESS FOR PREPARING POLY-O-HYDROXYAMIDES, PROCESS FOR PREPARING POLYBENZOXAZOLES, AND PROCESSES FOR PRODUCING AN ELECTRONIC COMPONENT
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Patent #:
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Issue Dt:
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09/12/2006
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Application #:
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10424507
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Filing Dt:
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04/28/2003
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Publication #:
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Pub Dt:
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12/09/2004
| | | | |
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Title:
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METHOD FOR FABRICATING A PATTERNED LAYER ON A SEMICONDUCTOR SUBSTRATE
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Patent #:
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Issue Dt:
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02/13/2007
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Application #:
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10425002
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Filing Dt:
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04/28/2003
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Publication #:
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Pub Dt:
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03/18/2004
| | | | |
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Title:
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READING EXTENDED DATA BURST FROM MEMORY
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Patent #:
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Issue Dt:
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11/14/2006
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Application #:
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10425224
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Filing Dt:
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04/29/2003
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Publication #:
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Pub Dt:
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11/04/2004
| | | | |
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Title:
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METHOD AND APPARATUS FOR MASKING KNOWN FAILS DURING MEMORY TESTS READOUTS
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Patent #:
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Issue Dt:
|
03/28/2006
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Application #:
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10425233
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Filing Dt:
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04/29/2003
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Publication #:
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Pub Dt:
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10/30/2003
| | | | |
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Title:
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PROCESS FOR PRODUCING HARD MASKS
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Patent #:
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Issue Dt:
|
11/23/2004
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Application #:
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10425280
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Filing Dt:
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04/29/2003
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Publication #:
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Pub Dt:
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01/15/2004
| | | | |
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Title:
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RAM MEMORY CIRCUIT AND METHOD FOR CONTROLLING THE SAME
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Patent #:
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Issue Dt:
|
03/15/2005
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Application #:
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10425460
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Filing Dt:
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04/29/2003
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Publication #:
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Pub Dt:
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12/11/2003
| | | | |
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Title:
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SURFACE-FUNCTIONALIZED INORGANIC SEMICONDUCTOR PARTICLES AS ELECTRICAL SEMICONDUCTORS FOR MICROELECTRONICS APPLICATIONS
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Patent #:
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Issue Dt:
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10/11/2005
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Application #:
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10425461
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Filing Dt:
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04/29/2003
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Publication #:
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Pub Dt:
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02/12/2004
| | | | |
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Title:
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METHOD FOR PATTERNING CERAMIC LAYERS
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Patent #:
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Issue Dt:
|
08/02/2005
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Application #:
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10427962
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Filing Dt:
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05/02/2003
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Publication #:
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Pub Dt:
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11/04/2004
| | | | |
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Title:
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SEMICONDUCTOR DEVICE WITH PEROVSKITE CAPACITOR
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Patent #:
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Issue Dt:
|
07/06/2004
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Application #:
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10429158
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Filing Dt:
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05/02/2003
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Publication #:
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Pub Dt:
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01/08/2004
| | | | |
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Title:
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STORAGE CIRCUIT
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Patent #:
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Issue Dt:
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03/22/2005
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Application #:
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10429577
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Filing Dt:
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05/05/2003
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Publication #:
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Pub Dt:
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12/18/2003
| | | | |
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Title:
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METHOD OF INCREASING AN INTERNAL OPERATING VOLTAGE FOR AN INTEGRATED CIRCUIT, AND INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
|
04/05/2005
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Application #:
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10429578
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Filing Dt:
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05/05/2003
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Publication #:
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Pub Dt:
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11/27/2003
| | | | |
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Title:
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TEST CONFIGURATION WITH AUTOMATIC TEST MACHINE AND INTEGRATED CIRCUIT AND METHOD FOR DETERMINING THE TIME BEHAVIOR OF AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
|
10/02/2007
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Application #:
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10429579
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Filing Dt:
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05/05/2003
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Publication #:
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Pub Dt:
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11/20/2003
| | | | |
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Title:
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METHOD AND AUXILIARY DEVICE FOR TESTING A RAM MEMORY CIRCUIT
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Patent #:
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Issue Dt:
|
03/15/2005
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Application #:
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10431422
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Filing Dt:
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05/07/2003
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Publication #:
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Pub Dt:
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11/13/2003
| | | | |
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Title:
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MEMORY CIRCUIT, METHOD FOR MANUFACTURING AND METHOD FOR OPERATING THE SAME
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Patent #:
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Issue Dt:
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08/09/2005
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Application #:
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10431425
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Filing Dt:
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05/06/2003
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Publication #:
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Pub Dt:
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11/20/2003
| | | | |
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Title:
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METHOD FOR FABRICATING A TRANSISTOR WITH A GATE STRUCTURE
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