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Reel/Frame:	023821/0535			Pages:	393
		Recorded:	01/15/2010
Attorney Dkt #:	609612800100
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 277
Page 1 of 3
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Patent #:	5846884	Issue Dt:	12/08/1998	Application #:	08879727	Filing Dt:	06/20/1997
Title:	METHODS FOR METAL ETCHING WITH REDUCED SIDEWALL BUILD UP DURING INTEGRATED CIRCUIT MANUFACTURING

Patent #:	6140236	Issue Dt:	10/31/2000	Application #:	09063094	Filing Dt:	04/21/1998
Title:	HIGH THROUGHPUT A1-CU THIN FILM SPUTTERING PROCESS ON SMALL CONTACT VIA FOR MANUFACTURABLE BEOL WIRING

Patent #:	6303506	Issue Dt:	10/16/2001	Application #:	09409464	Filing Dt:	09/30/1999
Title:	COMPOSITIONS FOR AND METHOD OF REDUCING/ELIMINATING SCRATCHES AND DEFECTS IN SILICON DIOXIDE DURING CMP PROCESS

Patent #:	6320803	Issue Dt:	11/20/2001	Application #:	09533226	Filing Dt:	03/23/2000
Title:	Method and apparatus for improving the testing, yield and performance of very large scale integratedcircuits

Patent #:	6461226	Issue Dt:	10/08/2002	Application #:	09654661	Filing Dt:	09/05/2000
Title:	CHEMICAL MECHANICAL POLISHING OF A METAL LAYER USING A COMPOSITE POLISHING PAD

Patent #:	7187602	Issue Dt:	03/06/2007	Application #:	10250211	Filing Dt:	06/13/2003
Publication #:	US20030179616	Pub Dt:	09/25/2003
Title:	REDUCING MEMORY FAILURES IN INTEGRATED CIRCUITS

Patent #:	6826099	Issue Dt:	11/30/2004	Application #:	10301529	Filing Dt:	11/20/2002
Publication #:	US20040095819	Pub Dt:	05/20/2004
Title:	2T2C SIGNAL MARGIN TEST MODE USING A DEFINED CHARGE AND DISCHARGE OF BL AND /BL

Patent #:	6731554	Issue Dt:	05/04/2004	Application #:	10301546	Filing Dt:	11/20/2002
Publication #:	US20040095820	Pub Dt:	05/20/2004
Title:	2T2C SIGNAL MARGIN TEST MODE USING RESISTIVE ELEMENT

Patent #:	6876590	Issue Dt:	04/05/2005	Application #:	10301548	Filing Dt:	11/20/2002
Publication #:	US20040095821	Pub Dt:	05/20/2004
Title:	2T2C SIGNAL MARGIN TEST MODE USING A DEFINED CHARGE EXCHANGE BETWEEN BL AND/BL

Patent #:	6794282	Issue Dt:	09/21/2004	Application #:	10305063	Filing Dt:	11/27/2002
Publication #:	US20040102001	Pub Dt:	05/27/2004
Title:	THREE LAYER ALUMINUM DEPOSITION PROCESS FOR HIGH ASPECT RATIO CL CONTACTS

Patent #:	6946735	Issue Dt:	09/20/2005	Application #:	10307257	Filing Dt:	11/29/2002
Publication #:	US20040104471	Pub Dt:	06/03/2004
Title:	SIDE-WALL BARRIER STRUCTURE AND METHOD OF FABRICATION

Patent #:	6709947	Issue Dt:	03/23/2004	Application #:	10314548	Filing Dt:	12/06/2002
Title:	METHOD OF AREA ENHANCEMENT IN CAPACITOR PLATES

Patent #:	6774691	Issue Dt:	08/10/2004	Application #:	10337606	Filing Dt:	01/07/2003
Publication #:	US20040130365	Pub Dt:	07/08/2004
Title:	HIGH RESOLUTION INTERLEAVED DELAY CHAIN

Patent #:	NONE	Issue Dt:		Application #:	10339157	Filing Dt:	01/09/2003
Publication #:	US20030104697	Pub Dt:	06/05/2003
Title:	Dry clean method instead of traditional wet clean after metal etch

Patent #:	6861872	Issue Dt:	03/01/2005	Application #:	10358581	Filing Dt:	02/05/2003
Publication #:	US20040150423	Pub Dt:	08/05/2004
Title:	VOLTAGE DOWN CONVERTER FOR LOW VOLTAGE OPERATION

Patent #:	7145216	Issue Dt:	12/05/2006	Application #:	10361989	Filing Dt:	02/11/2003
Publication #:	US20040156156	Pub Dt:	08/12/2004
Title:	ANTIFUSE PROGRAMMING WITH RELAXED UPPER CURRENT LIMIT

Patent #:	6946889	Issue Dt:	09/20/2005	Application #:	10364716	Filing Dt:	02/11/2003
Publication #:	US20040160253	Pub Dt:	08/19/2004
Title:	SELF ALIGNMENT SYSTEM FOR COMPLEMENT CLOCKS

Patent #:	6947344	Issue Dt:	09/20/2005	Application #:	10376408	Filing Dt:	02/28/2003
Publication #:	US20040170075	Pub Dt:	09/02/2004
Title:	MEMORY DEVICE AND METHOD OF READING DATA FROM A MEMORY CELL

Patent #:	7098142	Issue Dt:	08/29/2006	Application #:	10377083	Filing Dt:	02/26/2003
Publication #:	US20040164050	Pub Dt:	08/26/2004
Title:	METHOD OF ETCHING FERROELECTRIC DEVICES

Patent #:	6914844	Issue Dt:	07/05/2005	Application #:	10378472	Filing Dt:	03/03/2003
Publication #:	US20040174762	Pub Dt:	09/09/2004
Title:	DEEP POWER DOWN SWITCH FOR MEMORY DEVICE

Patent #:	6847092	Issue Dt:	01/25/2005	Application #:	10383191	Filing Dt:	03/06/2003
Publication #:	US20040173868	Pub Dt:	09/09/2004
Title:	MICROELECTRONIC CAPACITOR STRUCTURE WITH RADIAL CURRENT FLOW

Patent #:	6825707	Issue Dt:	11/30/2004	Application #:	10384860	Filing Dt:	03/10/2003
Publication #:	US20040178827	Pub Dt:	09/16/2004
Title:	CURRENT MODE LOGIC (CML) CIRCUIT CONCEPT FOR A VARIABLE DELAY ELEMENT

Patent #:	8934597	Issue Dt:	01/13/2015	Application #:	10386974	Filing Dt:	03/12/2003
Publication #:	US20040179640	Pub Dt:	09/16/2004
Title:	Multiple delay locked loop integration system and method

Patent #:	6909642	Issue Dt:	06/21/2005	Application #:	10387435	Filing Dt:	03/14/2003
Publication #:	US20040179417	Pub Dt:	09/16/2004
Title:	SELF TRIMMING VOLTAGE GENERATOR

Patent #:	6819142	Issue Dt:	11/16/2004	Application #:	10387733	Filing Dt:	03/13/2003
Publication #:	US20040178828	Pub Dt:	09/16/2004
Title:	CIRCUIT FOR TRANSFORMING A DIFFERENTIAL MODE SIGNAL INTO A SINGLE ENDED SIGNAL WITH REDUCED STANDBY CURRENT CONSUMPTION

Patent #:	6853229	Issue Dt:	02/08/2005	Application #:	10391850	Filing Dt:	03/19/2003
Publication #:	US20040183580	Pub Dt:	09/23/2004
Title:	CIRCUIT FOR TRANSFORMING A SINGLE ENDED SIGNAL INTO A DIFFERENTIAL MODE SIGNAL

Patent #:	6847225	Issue Dt:	01/25/2005	Application #:	10394779	Filing Dt:	03/21/2003
Publication #:	US20040183565	Pub Dt:	09/23/2004
Title:	CML (CURRENT MODE LOGIC) OCD (OFF CHIP DRIVER) - ODT (ON DIE TERMINATION) CIRCUIT FOR BIDIRECTIONAL DATA TRANSMISSION

Patent #:	6940773	Issue Dt:	09/06/2005	Application #:	10404561	Filing Dt:	04/02/2003
Publication #:	US20040196718	Pub Dt:	10/07/2004
Title:	METHOD AND SYSTEM FOR MANUFACTURING DRAMS WITH REDUCED SELF-REFRESH CURRENT REQUIREMENTS

Patent #:	6813193	Issue Dt:	11/02/2004	Application #:	10406019	Filing Dt:	04/02/2003
Publication #:	US20040196699	Pub Dt:	10/07/2004
Title:	MEMORY DEVICE AND METHOD OF OUTPUTTING DATA FROM A MEMORY DEVICE

Patent #:	6823713	Issue Dt:	11/30/2004	Application #:	10411728	Filing Dt:	04/11/2003
Publication #:	US20040200261	Pub Dt:	10/14/2004
Title:	SCANNING TIP ORIENTATION ADJUSTMENT METHOD FOR ATOMIC FORCE MICROSCOPY

Patent #:	6807084	Issue Dt:	10/19/2004	Application #:	10418734	Filing Dt:	04/17/2003
Publication #:	US20040208043	Pub Dt:	10/21/2004
Title:	FERAM MEMORY DEVICE

Patent #:	7016027	Issue Dt:	03/21/2006	Application #:	10431368	Filing Dt:	05/08/2003
Publication #:	US20040223145	Pub Dt:	11/11/2004
Title:	SYSTEM AND METHOD FOR QUANTIFYING ERRORS IN AN ALTERNATING PHASE SHIFT MASK

Patent #:	6838339	Issue Dt:	01/04/2005	Application #:	10456648	Filing Dt:	06/05/2003
Publication #:	US20040248365	Pub Dt:	12/09/2004
Title:	AREA-EFFICIENT STACK CAPACITOR

Patent #:	6807092	Issue Dt:	10/19/2004	Application #:	10461029	Filing Dt:	06/13/2003
Title:	MRAM CELL HAVING FRUSTRATED MAGNETIC RESERVOIRS

Patent #:	6930357	Issue Dt:	08/16/2005	Application #:	10463023	Filing Dt:	06/16/2003
Publication #:	US20040253773	Pub Dt:	12/16/2004
Title:	AN ACTIVE SOI STRUCTURE WITH A BODY CONTACT THROUGH AN INSULATOR

Patent #:	6806096	Issue Dt:	10/19/2004	Application #:	10464226	Filing Dt:	06/18/2003
Title:	INTEGRATION SCHEME FOR AVOIDING PLASMA DAMAGE IN MRAM TECHNOLOGY

Patent #:	7057253	Issue Dt:	06/06/2006	Application #:	10465144	Filing Dt:	06/19/2003
Publication #:	US20040256688	Pub Dt:	12/23/2004
Title:	COMBINATION OF INTRINSIC AND SHAPE ANISOTROPY FOR REDUCED SWITCHING FIELD FLUCTUATIONS

Patent #:	6783999	Issue Dt:	08/31/2004	Application #:	10600057	Filing Dt:	06/20/2003
Title:	SUBTRACTIVE STUD FORMATION FOR MRAM MANUFACTURING

Patent #:	6713802	Issue Dt:	03/30/2004	Application #:	10600661	Filing Dt:	06/20/2003
Title:	MAGNETIC TUNNEL JUNCTION PATTERNING USING SIC OR SIN

Patent #:	6849465	Issue Dt:	02/01/2005	Application #:	10600920	Filing Dt:	06/20/2003
Publication #:	US20040259274	Pub Dt:	12/23/2004
Title:	METHOD OF PATTERNING A MAGNETIC MEMORY CELL BOTTOM ELECTRODE BEFORE MAGNETIC STACK DEPOSITION

Patent #:	7221788	Issue Dt:	05/22/2007	Application #:	10611067	Filing Dt:	07/01/2003
Publication #:	US20050002554	Pub Dt:	01/06/2005
Title:	METHOD OF INSPECTING A MASK OR RETICLE FOR DETECTING A DEFECT, AND MASK OR RETICLE INSPECTION SYSTEM

Patent #:	6864151	Issue Dt:	03/08/2005	Application #:	10615630	Filing Dt:	07/09/2003
Publication #:	US20050009290	Pub Dt:	01/13/2005
Title:	METHOD OF FORMING SHALLOW TRENCH ISOLATION USING DEEP TRENCH ISOLATION

Patent #:	6839267	Issue Dt:	01/04/2005	Application #:	10618333	Filing Dt:	07/11/2003
Publication #:	US20050007804	Pub Dt:	01/13/2005
Title:	STRUCTURE AND METHOD OF MULTIPLEXING BITLINE SIGNALS WITHIN A MEMORY ARRAY

Patent #:	6937058	Issue Dt:	08/30/2005	Application #:	10620989	Filing Dt:	07/16/2003
Publication #:	US20050012519	Pub Dt:	01/20/2005
Title:	METHODS AND APPARATUS FOR ACTIVE TERMINATION OF HIGH-FREQUENCY SIGNALS

Patent #:	6839220	Issue Dt:	01/04/2005	Application #:	10623461	Filing Dt:	07/18/2003
Publication #:	US20050013091	Pub Dt:	01/20/2005
Title:	MULTI-LAYER BARRIER ALLOWING RECOVERY ANNEAL FOR FERROELECTRIC CAPACITORS

Patent #:	6937531	Issue Dt:	08/30/2005	Application #:	10624031	Filing Dt:	07/21/2003
Publication #:	US20050018497	Pub Dt:	01/27/2005
Title:	MEMORY DEVICE AND METHOD OF STORING FAIL ADDRESSES OF A MEMORY CELL

Patent #:	7101785	Issue Dt:	09/05/2006	Application #:	10625483	Filing Dt:	07/22/2003
Publication #:	US20050020054	Pub Dt:	01/27/2005
Title:	FORMATION OF A CONTACT IN A DEVICE, AND THE DEVICE INCLUDING THE CONTACT

Patent #:	6975550	Issue Dt:	12/13/2005	Application #:	10625962	Filing Dt:	07/24/2003
Publication #:	US20050018469	Pub Dt:	01/27/2005
Title:	ARRAY TRANSISTOR AMPLIFICATION METHOD AND APPARATUS FOR DYNAMIC RANDOM ACCESS MEMORY

Patent #:	6913990	Issue Dt:	07/05/2005	Application #:	10628149	Filing Dt:	07/28/2003
Publication #:	US20050026341	Pub Dt:	02/03/2005
Title:	METHOD OF FORMING ISOLATION DUMMY FILL STRUCTURES

Patent #:	6867053	Issue Dt:	03/15/2005	Application #:	10629326	Filing Dt:	07/28/2003
Publication #:	US20050023582	Pub Dt:	02/03/2005
Title:	FABRICATION OF A FERAM CAPACITOR USING A NOBLE METAL HARDMASK

Patent #:	6958626	Issue Dt:	10/25/2005	Application #:	10631394	Filing Dt:	07/31/2003
Publication #:	US20050024090	Pub Dt:	02/03/2005
Title:	OFF CHIP DRIVER

Patent #:	6999887	Issue Dt:	02/14/2006	Application #:	10636369	Filing Dt:	08/06/2003
Publication #:	US20050033541	Pub Dt:	02/10/2005
Title:	MEMORY CELL SIGNAL WINDOW TESTING APPARATUS

Patent #:	7062748	Issue Dt:	06/13/2006	Application #:	10648493	Filing Dt:	08/25/2003
Publication #:	US20050050511	Pub Dt:	03/03/2005
Title:	SYSTEM AND METHOD OF CORRECTING MASK RULE VIOLATIONS AFTER OPTICAL PROXIMITY CORRECTION

Patent #:	7199002	Issue Dt:	04/03/2007	Application #:	10651614	Filing Dt:	08/29/2003
Publication #:	US20050045932	Pub Dt:	03/03/2005
Title:	PROCESS FOR FABRICATION OF A FERROELECTRIC CAPACITOR

Patent #:	7170798	Issue Dt:	01/30/2007	Application #:	10652266	Filing Dt:	08/29/2003
Publication #:	US20050050262	Pub Dt:	03/03/2005
Title:	CONTROLLED SUBSTRATE VOLTAGE FOR MEMORY SWITCHES

Patent #:	6970395	Issue Dt:	11/29/2005	Application #:	10658130	Filing Dt:	09/08/2003
Publication #:	US20050052943	Pub Dt:	03/10/2005
Title:	MEMORY DEVICE AND METHOD OF READING DATA FROM A MEMORY DEVICE

Patent #:	7134102	Issue Dt:	11/07/2006	Application #:	10661295	Filing Dt:	09/12/2003
Publication #:	US20050060672	Pub Dt:	03/17/2005
Title:	AUTOMATED LAYOUT TRANSFORMATION SYSTEM AND METHOD

Patent #:	7231488	Issue Dt:	06/12/2007	Application #:	10663151	Filing Dt:	09/15/2003
Publication #:	US20050060488	Pub Dt:	03/17/2005
Title:	SELF-REFRESH SYSTEM AND METHOD FOR DYNAMIC RANDOM ACCESS MEMORY

Patent #:	7183121	Issue Dt:	02/27/2007	Application #:	10673053	Filing Dt:	09/26/2003
Publication #:	US20050067642	Pub Dt:	03/31/2005
Title:	PROCESS FOR FABRICATION OF A FERROCAPACITOR

Patent #:	6947306	Issue Dt:	09/20/2005	Application #:	10674304	Filing Dt:	09/30/2003
Publication #:	US20050078500	Pub Dt:	04/14/2005
Title:	BACKSIDE OF CHIP IMPLEMENTATION OF REDUNDANCY FUSES AND CONTACT PADS

Patent #:	6956782	Issue Dt:	10/18/2005	Application #:	10674905	Filing Dt:	09/30/2003
Publication #:	US20050068826	Pub Dt:	03/31/2005
Title:	SELECTIVE BANK REFRESH

Patent #:	6831320	Issue Dt:	12/14/2004	Application #:	10675054	Filing Dt:	09/30/2003
Publication #:	US20040062124	Pub Dt:	04/01/2004
Title:	MEMORY CELL CONFIGURATION FOR A DRAM MEMORY WITH A CONTACT BIT TERMINAL FOR TWO TRENCH CAPACITORS OF DIFFERENT ROWS

Patent #:	7061035	Issue Dt:	06/13/2006	Application #:	10677852	Filing Dt:	10/01/2003
Publication #:	US20050082583	Pub Dt:	04/21/2005
Title:	SELF-ALIGNED VO-CONTACT FOR CELL SIZE REDUCTION

Patent #:	6933206	Issue Dt:	08/23/2005	Application #:	10683668	Filing Dt:	10/10/2003
Publication #:	US20050079730	Pub Dt:	04/14/2005
Title:	TRENCH ISOLATION EMPLOYING A HIGH ASPECT RATIO TRENCH

Patent #:	7084966	Issue Dt:	08/01/2006	Application #:	10689241	Filing Dt:	10/20/2003
Publication #:	US20050083514	Pub Dt:	04/21/2005
Title:	OPTICAL MEASUREMENT OF DEVICE FEATURES USING LENSLET ARRAY ILLUMINATION

Patent #:	7183131	Issue Dt:	02/27/2007	Application #:	10712767	Filing Dt:	11/12/2003
Publication #:	US20050040847	Pub Dt:	02/24/2005
Title:	PROCESS FOR PRODUCING A NANOELEMENT ARRANGEMENT, AND NANOELEMENT ARRANGEMENT

Patent #:	NONE	Issue Dt:		Application #:	10721225	Filing Dt:	11/26/2003
Publication #:	US20040152317	Pub Dt:	08/05/2004
Title:	METHOD AND STRUCTURES FOR INCREASING THE STRUCTURE DENSITY AND THE STORAGE CAPACITANCE IN A SEMICONDUCTOR WAFER

Patent #:	6964912	Issue Dt:	11/15/2005	Application #:	10721752	Filing Dt:	11/26/2003
Publication #:	US20040157390	Pub Dt:	08/12/2004
Title:	METHOD FOR FABRICATING A SEMICONDUCTOR STRUCTURE

Patent #:	6916721	Issue Dt:	07/12/2005	Application #:	10722360	Filing Dt:	11/26/2003
Publication #:	US20040197988	Pub Dt:	10/07/2004
Title:	METHOD FOR FABRICATING A TRENCH CAPACITOR WITH AN INSULATION COLLAR

Patent #:	6911059	Issue Dt:	06/28/2005	Application #:	10723630	Filing Dt:	11/26/2003
Publication #:	US20040116054	Pub Dt:	06/17/2004
Title:	ABRASIVE PAD AND PROCESS FOR THE WET-CHEMICAL GRINDING OF A SUBSTRATE SURFACE

Patent #:	6977427	Issue Dt:	12/20/2005	Application #:	10723906	Filing Dt:	11/26/2003
Publication #:	US20040108585	Pub Dt:	06/10/2004
Title:	ELECTRONIC COMPONENT HAVING STACKED SEMICONDUCTOR CHIPS IN PARALLEL, AND A METHOD FOR PRODUCING THE COMPONENT

Patent #:	6919234	Issue Dt:	07/19/2005	Application #:	10724007	Filing Dt:	11/26/2003
Publication #:	US20050003647	Pub Dt:	01/06/2005
Title:	METHOD FOR PRODUCING AN ANTIFUSE IN A SUBSTRATE AND AN ANTIFUSE STRUCTURE FOR INTEGRATION IN A SUBSTRATE

Patent #:	7199060	Issue Dt:	04/03/2007	Application #:	10724141	Filing Dt:	12/01/2003
Publication #:	US20040152332	Pub Dt:	08/05/2004
Title:	METHOD FOR PATTERNING DIELECTRIC LAYERS ON SEMICONDUCTOR SUBSTRATES

Patent #:	7251772	Issue Dt:	07/31/2007	Application #:	10732402	Filing Dt:	12/11/2003
Publication #:	US20040136249	Pub Dt:	07/15/2004
Title:	CIRCUIT ARRANGEMENT HAVING A NUMBER OF INTEGRATED CIRCUIT COMPONENTS ON A CARRIER SUBSTRATE AND METHOD FOR TESTING A CIRCUIT ARRANGEMENT OF THIS TYPE

Patent #:	7005355	Issue Dt:	02/28/2006	Application #:	10735411	Filing Dt:	12/12/2003
Publication #:	US20040147072	Pub Dt:	07/29/2004
Title:	METHOD FOR FABRICATING SEMICONDUCTOR MEMORIES WITH CHARGE TRAPPING MEMORY CELLS

Patent #:	6900626	Issue Dt:	05/31/2005	Application #:	10736506	Filing Dt:	12/17/2003
Publication #:	US20040124824	Pub Dt:	07/01/2004
Title:	VOLTAGE GENERATOR ARRANGEMENT

Patent #:	6927557	Issue Dt:	08/09/2005	Application #:	10736507	Filing Dt:	12/17/2003
Publication #:	US20040130310	Pub Dt:	07/08/2004
Title:	VOLTAGE GENERATOR ARRANGEMENT

Patent #:	7054180	Issue Dt:	05/30/2006	Application #:	10737481	Filing Dt:	12/16/2003
Publication #:	US20050196909	Pub Dt:	09/08/2005
Title:	METHOD AND CIRCUIT FOR ADJUSTING A RESISTANCE IN AN INTEGRATED CIRCUIT

Patent #:	7251758	Issue Dt:	07/31/2007	Application #:	10738118	Filing Dt:	12/18/2003
Publication #:	US20040196022	Pub Dt:	10/07/2004
Title:	SEMICONDUCTOR DEVICE TESTING APPARATUS, SYSTEM, AND METHOD FOR TESTING THE CONTACTING WITH SEMICONDUCTOR DEVICES POSITIONED ONE UPON THE OTHER

Patent #:	6944573	Issue Dt:	09/13/2005	Application #:	10740377	Filing Dt:	12/18/2003
Publication #:	US20040220754	Pub Dt:	11/04/2004
Title:	METHOD AND APPARATUS FOR THE ANALYSIS OF SCRATCHES ON SEMICONDUCTOR WAFERS

Patent #:	6992348	Issue Dt:	01/31/2006	Application #:	10741970	Filing Dt:	12/19/2003
Publication #:	US20040164345	Pub Dt:	08/26/2004
Title:	SEMICONDUCTOR MEMORY WITH VERTICAL CHARGE-TRAPPING MEMORY CELLS AND FABRICATION

Patent #:	7335936	Issue Dt:	02/26/2008	Application #:	10744051	Filing Dt:	12/23/2003
Publication #:	US20040197989	Pub Dt:	10/07/2004
Title:	DRAM MEMORY HAVING VERTICALLY ARRANGED SELECTION TRANSISTORS

Patent #:	7372093	Issue Dt:	05/13/2008	Application #:	10744056	Filing Dt:	12/23/2003
Publication #:	US20050056873	Pub Dt:	03/17/2005
Title:	DRAM MEMORY WITH VERTICALLY ARRANGED SELECTION TRANSISTORS

Patent #:	7289231	Issue Dt:	10/30/2007	Application #:	10744067	Filing Dt:	12/24/2003
Publication #:	US20040194039	Pub Dt:	09/30/2004
Title:	APPARATUS AND METHOD FOR DETERMINING PHYSICAL PROPERTIES OF A MASK BLANK

Patent #:	7049854	Issue Dt:	05/23/2006	Application #:	10745928	Filing Dt:	12/23/2003
Publication #:	US20040178830	Pub Dt:	09/16/2004
Title:	SENSE AMPLIFIER HAVING LOW-VOLTAGE THRESHOLD TRANSISTORS

Patent #:	7022549	Issue Dt:	04/04/2006	Application #:	10747670	Filing Dt:	12/30/2003
Publication #:	US20040191958	Pub Dt:	09/30/2004
Title:	METHOD FOR CONNECTING AN INTEGRATED CIRCUIT TO A SUBSTRATE AND CORRESPONDING ARRANGEMENT

Patent #:	7002222	Issue Dt:	02/21/2006	Application #:	10753407	Filing Dt:	01/09/2004
Publication #:	US20050029602	Pub Dt:	02/10/2005
Title:	INTEGRATED SEMICONDUCTOR MEMORY CIRCUIT AND METHOD OF MANUFACTURING THE SAME

Patent #:	7150946	Issue Dt:	12/19/2006	Application #:	10753604	Filing Dt:	01/08/2004
Publication #:	US20050153213	Pub Dt:	07/14/2005
Title:	METHOD FOR THE REPAIR OF DEFECTS IN PHOTOLITHOGRAPHIC MASKS FOR PATTERNING SEMICONDUCTOR WAFERS

Patent #:	7231562	Issue Dt:	06/12/2007	Application #:	10754455	Filing Dt:	01/09/2004
Publication #:	US20040260987	Pub Dt:	12/23/2004
Title:	MEMORY MODULE, TEST SYSTEM AND METHOD FOR TESTING ONE OR A PLURALITY OF MEMORY MODULES

Patent #:	7049228	Issue Dt:	05/23/2006	Application #:	10756360	Filing Dt:	01/14/2004
Publication #:	US20040192031	Pub Dt:	09/30/2004
Title:	METHOD FOR INTRODUCING STRUCTURES WHICH HAVE DIFFERENT DIMENSIONS INTO A SUBSTRATE

Patent #:	7060534	Issue Dt:	06/13/2006	Application #:	10757549	Filing Dt:	01/15/2004
Publication #:	US20040197978	Pub Dt:	10/07/2004
Title:	HOUSING FOR SEMICONDUCTOR DEVICES, SEMICONDUCTOR DEVICE PIN, AND METHOD FOR THE MANUFACTURING OF PINS

Patent #:	6970389	Issue Dt:	11/29/2005	Application #:	10757594	Filing Dt:	01/15/2004
Publication #:	US20040156254	Pub Dt:	08/12/2004
Title:	INTEGRATED MEMORY

Patent #:	6917549	Issue Dt:	07/12/2005	Application #:	10759153	Filing Dt:	01/20/2004
Publication #:	US20040156253	Pub Dt:	08/12/2004
Title:	INTEGRATED MEMORY AND METHOD FOR OPERATING IT

Patent #:	7136320	Issue Dt:	11/14/2006	Application #:	10761127	Filing Dt:	01/20/2004
Publication #:	US20040208074	Pub Dt:	10/21/2004
Title:	METHOD AND REGULATING CIRCUIT FOR REFRESHING DYNAMIC MEMORY CELLS

Patent #:	6914837	Issue Dt:	07/05/2005	Application #:	10761242	Filing Dt:	01/22/2004
Publication #:	US20040208073	Pub Dt:	10/21/2004
Title:	DRAM MEMORY WITH A SHARED SENSE AMPLIFIER STRUCTURE

Patent #:	7087485	Issue Dt:	08/08/2006	Application #:	10765052	Filing Dt:	01/28/2004
Publication #:	US20050037565	Pub Dt:	02/17/2005
Title:	METHOD OF FABRICATING AN OXIDE COLLAR FOR A TRENCH CAPACITOR

Patent #:	7074660	Issue Dt:	07/11/2006	Application #:	10765910	Filing Dt:	01/29/2004
Publication #:	US20050014318	Pub Dt:	01/20/2005
Title:	FINFET DEVICE AND METHOD OF FABRICATION

Patent #:	NONE	Issue Dt:		Application #:	10766053	Filing Dt:	01/28/2004
Publication #:	US20050164469	Pub Dt:	07/28/2005
Title:	Method for N+ doping of amorphous silicon and polysilicon electrodes in deep trenches

Patent #:	7214610	Issue Dt:	05/08/2007	Application #:	10768241	Filing Dt:	01/30/2004
Publication #:	US20040242007	Pub Dt:	12/02/2004
Title:	PROCESS FOR PRODUCING ALUMINUM-FILLED CONTACT HOLES

100

Patent #:	7120077	Issue Dt:	10/10/2006	Application #:	10776178	Filing Dt:	02/12/2004
Publication #:	US20040184337	Pub Dt:	09/23/2004
Title:	MEMORY MODULE HAVING A PLURALITY OF INTEGRATED MEMORY COMPONENTS

Assignor

INFINEON TECHNOLOGIES AG

Exec Dt:

04/25/2006

Assignee

QIMONDA AG

GUSTAV-HEINEMANN-RING 212

MUNICH, GERMANY 81739

Correspondence name and address
	JONATHAN BOCKMAN
	C/O MORRISON AND FOERSTER LLP
	1650 TYSONS BLVD. SUITE 400
	MCLEAN, VA 22102

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