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Patent Assignment Details

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Reel/Frame:	023832/0001			Pages:	386
		Recorded:	01/15/2010
Attorney Dkt #:	609612800100
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 29

Patent #:	6787831	Issue Dt:	09/07/2004	Application #:	10050246	Filing Dt:	01/15/2002
Publication #:	US20030132469	Pub Dt:	07/17/2003
Title:	BARRIER STACK WITH IMPROVED BARRIER PROPERTIES

Patent #:	6687150	Issue Dt:	02/03/2004	Application #:	10064955	Filing Dt:	09/04/2002
Title:	REFERENCE VOLTAGE GENERATION FOR MEMORY CIRCUITS

Patent #:	6614642	Issue Dt:	09/02/2003	Application #:	10065122	Filing Dt:	09/19/2002
Title:	CAPACITOR OVER PLUG STRUCTURE

Patent #:	6724026	Issue Dt:	04/20/2004	Application #:	10065123	Filing Dt:	09/19/2002
Publication #:	US20040056286	Pub Dt:	03/25/2004
Title:	MEMORY ARCHITECTURE WITH MEMORY CELL GROUPS

Patent #:	6639824	Issue Dt:	10/28/2003	Application #:	10065126	Filing Dt:	09/19/2002
Title:	MEMORY ARCHITECTURE

Patent #:	6621683	Issue Dt:	09/16/2003	Application #:	10065127	Filing Dt:	09/19/2002
Title:	MEMORY CELLS WITH IMPROVED RELIABILITY

Patent #:	6707699	Issue Dt:	03/16/2004	Application #:	10065167	Filing Dt:	09/24/2002
Publication #:	US20040057273	Pub Dt:	03/25/2004
Title:	HISTORICAL INFORMATION STORAGE FOR INTEGRATED CIRCUITS

Patent #:	6903959	Issue Dt:	06/07/2005	Application #:	10065168	Filing Dt:	09/24/2002
Publication #:	US20040057275	Pub Dt:	03/25/2004
Title:	SENSING OF MEMORY INTEGRATED CIRCUITS

Patent #:	6920059	Issue Dt:	07/19/2005	Application #:	10065921	Filing Dt:	11/29/2002
Publication #:	US20040105293	Pub Dt:	06/03/2004
Title:	REDUCING EFFECTS OF NOISE COUPLING IN INTEGRATED CIRCUITS WITH MEMORY ARRAYS

Patent #:	6940111	Issue Dt:	09/06/2005	Application #:	10065922	Filing Dt:	11/29/2002
Publication #:	US20040104754	Pub Dt:	06/03/2004
Title:	RADIATION PROTECTION IN INTEGRATED CIRCUITS

Patent #:	6584009	Issue Dt:	06/24/2003	Application #:	10103360	Filing Dt:	03/21/2002
Title:	MEMORY INTEGRATED CIRCUIT WITH IMPROVED RELIABILITY

Patent #:	6954873	Issue Dt:	10/11/2005	Application #:	10115504	Filing Dt:	04/02/2002
Publication #:	US20030088801	Pub Dt:	05/08/2003
Title:	IMPLEMENTATION OF WAIT-STATES

Patent #:	6856560	Issue Dt:	02/15/2005	Application #:	10133764	Filing Dt:	04/26/2002
Publication #:	US20030202386	Pub Dt:	10/30/2003
Title:	REDUNDANCY IN CHAINED MEMORY ARCHITECTURES

Patent #:	6687171	Issue Dt:	02/03/2004	Application #:	10133919	Filing Dt:	04/26/2002
Publication #:	US20030202387	Pub Dt:	10/30/2003
Title:	FLEXIBLE REDUNDANCY FOR MEMORIES

Patent #:	6583507	Issue Dt:	06/24/2003	Application #:	10134071	Filing Dt:	04/26/2002
Title:	BARRIER FOR CAPACITOR OVER PLUG STRUCTURES

Patent #:	6731529	Issue Dt:	05/04/2004	Application #:	10161907	Filing Dt:	06/04/2002
Publication #:	US20030223263	Pub Dt:	12/04/2003
Title:	VARIABLE CAPACITANCES FOR MEMORY CELLS WITHIN A CELL GROUP

Patent #:	6821865	Issue Dt:	11/23/2004	Application #:	10248233	Filing Dt:	12/30/2002
Publication #:	US20040126986	Pub Dt:	07/01/2004
Title:	IMPROVED DEEP ISOLATION TRENCHES

Patent #:	6800890	Issue Dt:	10/05/2004	Application #:	10248234	Filing Dt:	12/30/2002
Publication #:	US20040232457	Pub Dt:	11/25/2004
Title:	MEMORY ARCHITECTURE WITH SERIES GROUPED BY CELLS

Patent #:	6815234	Issue Dt:	11/09/2004	Application #:	10248253	Filing Dt:	12/31/2002
Publication #:	US20040124452	Pub Dt:	07/01/2004
Title:	REDUCING STRESS IN INTEGRATED CIRCUITS

Patent #:	6897501	Issue Dt:	05/24/2005	Application #:	10248897	Filing Dt:	02/28/2003
Publication #:	US20040169211	Pub Dt:	09/02/2004
Title:	AVOIDING SHORTING IN CAPACITORS

Patent #:	6827635	Issue Dt:	12/07/2004	Application #:	10248949	Filing Dt:	03/05/2003
Publication #:	US20040185756	Pub Dt:	09/23/2004
Title:	METHOD OF PLANARIZING SUBSTRATES

Patent #:	6932674	Issue Dt:	08/23/2005	Application #:	10248950	Filing Dt:	03/05/2003
Publication #:	US20040176015	Pub Dt:	09/09/2004
Title:	METHOD OF DETERMINING THE ENDPOINT OF A PLANARIZATION PROCESS

Patent #:	7170173	Issue Dt:	01/30/2007	Application #:	10249528	Filing Dt:	04/17/2003
Publication #:	US20040207086	Pub Dt:	10/21/2004
Title:	MAGNETICALLY LINED CONDUCTORS

Patent #:	6768150	Issue Dt:	07/27/2004	Application #:	10249532	Filing Dt:	04/17/2003
Title:	MAGNETIC MEMORY

Patent #:	7009230	Issue Dt:	03/07/2006	Application #:	10604323	Filing Dt:	07/10/2003
Publication #:	US20040178431	Pub Dt:	09/16/2004
Title:	BARRIER STACK WITH IMPROVED BARRIER PROPERTIES

Patent #:	7157329	Issue Dt:	01/02/2007	Application #:	11053508	Filing Dt:	02/08/2005
Publication #:	US20050158961	Pub Dt:	07/21/2005
Title:	TRENCH CAPACITOR WITH BURIED STRAP

Assignor

Exec Dt:

04/25/2006

Assignee

GUSTAV-HEINEMANN-RING 212

MUNICH, GERMANY 81739

Correspondence name and address
	JONATHAN BOCKMAN
	C/O MORRISON & FOERSTER LLP
	1650 TYSONS BLVD. SUITE 400
	MCLEAN, VA 22102

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