Total properties:
249
Page
1
of
3
Pages:
1 2 3
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/26/2006
|
Application #:
|
10641812
|
Filing Dt:
|
08/15/2003
|
|
Publication #:
|
|
Pub Dt:
|
02/17/2005
| | | | |
|
Title:
|
REDUCED POWER CONSUMPTION IN INTEGRATED CIRCUITS WITH FUSE CONTROLLED REDUNDANT CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/18/2005
|
Application #:
|
10651281
|
Filing Dt:
|
08/28/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/03/2005
| | | | |
|
Title:
|
REFERENCE VOLTAGE DETECTOR FOR POWER-ON SEQUENCE IN A MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/05/2006
|
Application #:
|
10651753
|
Filing Dt:
|
08/29/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/03/2005
| | | | |
|
Title:
|
RELIABLE FERRO FUSE CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/04/2006
|
Application #:
|
10655757
|
Filing Dt:
|
09/05/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/10/2005
| | | | |
|
Title:
|
DEVICE FOR INHIBITING HYDROGEN DAMAGE IN FERROELECTRIC CAPACITOR DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/21/2005
|
Application #:
|
10672118
|
Filing Dt:
|
09/26/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/31/2005
| | | | |
|
Title:
|
RANDOM ACCESS MEMORY HAVING DRIVER FOR REDUCED LEAKAGE CURRENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/10/2006
|
Application #:
|
10672120
|
Filing Dt:
|
09/26/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/14/2005
| | | | |
|
Title:
|
MEMORY DEVICE HAVING MULTIPLE ARRAY STRUCTURE FOR INCREASED BANDWIDTH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/01/2005
|
Application #:
|
10672244
|
Filing Dt:
|
09/25/2003
|
|
Title:
|
MEMORY SYSTEM WITH REDUCED REFRESH CURRENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/23/2005
|
Application #:
|
10672246
|
Filing Dt:
|
09/25/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/31/2005
| | | | |
|
Title:
|
TEMPERATURE SENSOR SCHEME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/21/2006
|
Application #:
|
10672306
|
Filing Dt:
|
09/26/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/31/2005
| | | | |
|
Title:
|
METHOD FOR PRODUCING A FERROELECTRIC CAPACITOR THAT INCLUDES ETCHING WITH HARDMASKS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/05/2006
|
Application #:
|
10673626
|
Filing Dt:
|
09/29/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/31/2005
| | | | |
|
Title:
|
MEMORY DEVICE WITH A FLEXIBLE REDUCED DENSITY OPTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/18/2006
|
Application #:
|
10674177
|
Filing Dt:
|
09/29/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/31/2005
| | | | |
|
Title:
|
RANDOM ACCESS MEMORY WITH POST-AMBLE DATA STROBE SIGNAL NOISE REJECTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/13/2005
|
Application #:
|
10674386
|
Filing Dt:
|
10/01/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/07/2005
| | | | |
|
Title:
|
SYSTEM AND METHOD FOR AUTOMATICALLY-DETECTING SOFT ERRORS IN LATCHES OF AN INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/07/2006
|
Application #:
|
10675549
|
Filing Dt:
|
09/30/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/31/2005
| | | | |
|
Title:
|
ECHO CLOCK ON MEMORY SYSTEM HAVING WAIT INFORMATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/02/2005
|
Application #:
|
10676360
|
Filing Dt:
|
09/30/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/31/2005
| | | | |
|
Title:
|
DEVICE AND A METHOD FOR FORMING A FERROELECTRIC CAPACITOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/09/2006
|
Application #:
|
10677099
|
Filing Dt:
|
09/30/2003
|
|
Publication #:
|
|
Pub Dt:
|
03/31/2005
| | | | |
|
Title:
|
DEVICE AND A METHOD FOR FORMING A CAPACITOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/08/2008
|
Application #:
|
10678758
|
Filing Dt:
|
10/02/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/07/2005
| | | | |
|
Title:
|
METHOD FOR FORMING FERROCAPACITORS AND FERAM DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/02/2006
|
Application #:
|
10681647
|
Filing Dt:
|
10/08/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/14/2005
| | | | |
|
Title:
|
VOLTAGE TRIMMING CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/23/2005
|
Application #:
|
10683768
|
Filing Dt:
|
10/10/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/14/2005
| | | | |
|
Title:
|
METHOD AND CIRCUIT CONFIGURATION FOR DIGITIZING A SIGNAL IN AN INPUT BUFFER OF A DRAM DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/06/2005
|
Application #:
|
10683965
|
Filing Dt:
|
10/10/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/14/2005
| | | | |
|
Title:
|
REFERENCE CURRENT DISTRIBUTION IN MRAM DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/18/2006
|
Application #:
|
10685004
|
Filing Dt:
|
10/15/2003
|
|
Publication #:
|
|
Pub Dt:
|
04/21/2005
| | | | |
|
Title:
|
MASK AND METHOD FOR USING THE MASK IN LITHOGRAPHIC PROCESSING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/25/2005
|
Application #:
|
10692119
|
Filing Dt:
|
10/23/2003
|
|
Title:
|
METHOD AND CIRCUIT CONFIGURATION FOR MULTIPLE CHARGE RECYCLING DURING REFRESH OPERATIONS IN A DRAM DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/10/2006
|
Application #:
|
10702074
|
Filing Dt:
|
11/03/2003
|
|
Publication #:
|
|
Pub Dt:
|
05/05/2005
| | | | |
|
Title:
|
DEVICE AND METHOD FOR INHIBITING OXIDATION OF CONTACT PLUGS IN FERROELECTRIC CAPACITOR DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/10/2006
|
Application #:
|
10703870
|
Filing Dt:
|
11/07/2003
|
|
Publication #:
|
|
Pub Dt:
|
05/12/2005
| | | | |
|
Title:
|
FERROELECTRIC CAPACITOR DEVICES AND A METHOD FOR COMPENSATING FOR DAMAGE TO A CAPACITOR CAUSED BY ETCHING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/22/2006
|
Application #:
|
10704091
|
Filing Dt:
|
11/07/2003
|
|
Publication #:
|
|
Pub Dt:
|
05/12/2005
| | | | |
|
Title:
|
REFRESH FOR DYNAMIC CELLS WITH WEAK RETENTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/04/2005
|
Application #:
|
10706146
|
Filing Dt:
|
11/12/2003
|
|
Title:
|
LATCH SCHEME WITH INVALID COMMAND DETECTOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/21/2006
|
Application #:
|
10713239
|
Filing Dt:
|
11/13/2003
|
|
Publication #:
|
|
Pub Dt:
|
05/19/2005
| | | | |
|
Title:
|
FERROELECTRIC CAPACITOR DEVICES AND FERAM DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/23/2006
|
Application #:
|
10715142
|
Filing Dt:
|
11/17/2003
|
|
Publication #:
|
|
Pub Dt:
|
05/19/2005
| | | | |
|
Title:
|
CHARGE-TRAPPING MEMORY DEVICE INCLUDING HIGH PERMITTIVITY STRIPS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2008
|
Application #:
|
10715812
|
Filing Dt:
|
11/18/2003
|
|
Publication #:
|
|
Pub Dt:
|
05/19/2005
| | | | |
|
Title:
|
METHOD AND CIRCUIT CONFIGURATION FOR REFRESHING DATA IN A SEMICONDUCTOR MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/06/2007
|
Application #:
|
10716079
|
Filing Dt:
|
11/18/2003
|
|
Publication #:
|
|
Pub Dt:
|
05/19/2005
| | | | |
|
Title:
|
LOW RISE/FALL SKEWED INPUT BUFFER COMPENSATING PROCESS VARIATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/04/2006
|
Application #:
|
10716381
|
Filing Dt:
|
11/17/2003
|
|
Publication #:
|
|
Pub Dt:
|
08/05/2004
| | | | |
|
Title:
|
DUAL-PURPOSE SHIFT REGISTER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/04/2007
|
Application #:
|
10716749
|
Filing Dt:
|
11/19/2003
|
|
Publication #:
|
|
Pub Dt:
|
05/19/2005
| | | | |
|
Title:
|
INTERNAL VOLTAGE GENERATOR WITH TEMPERATURE CONTROL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/07/2006
|
Application #:
|
10716762
|
Filing Dt:
|
11/19/2003
|
|
Publication #:
|
|
Pub Dt:
|
05/19/2005
| | | | |
|
Title:
|
BACK-BIAS VOLTAGE GENERATOR WITH TEMPERATURE CONTROL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/03/2005
|
Application #:
|
10723211
|
Filing Dt:
|
11/26/2003
|
|
Publication #:
|
|
Pub Dt:
|
05/26/2005
| | | | |
|
Title:
|
DUAL POWER SENSING SCHEME FOR A MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/28/2006
|
Application #:
|
10727106
|
Filing Dt:
|
12/03/2003
|
|
Publication #:
|
|
Pub Dt:
|
06/09/2005
| | | | |
|
Title:
|
METHODS AND APPARATUS FOR ACTIVE TERMINATION OF HIGH-FREQUENCY SIGNALS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/18/2005
|
Application #:
|
10727406
|
Filing Dt:
|
12/04/2003
|
|
Publication #:
|
|
Pub Dt:
|
06/09/2005
| | | | |
|
Title:
|
RANDOM ACCESS MEMORY WITH OPTIONAL INACCESSIBLE MEMORY CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/05/2006
|
Application #:
|
10730443
|
Filing Dt:
|
12/08/2003
|
|
Publication #:
|
|
Pub Dt:
|
06/09/2005
| | | | |
|
Title:
|
CHIP TO CHIP INTERFACE FOR ENCODING DATA AND CLOCK SIGNALS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/26/2006
|
Application #:
|
10730445
|
Filing Dt:
|
12/08/2003
|
|
Publication #:
|
|
Pub Dt:
|
06/09/2005
| | | | |
|
Title:
|
CHIP TO CHIP INTERFACE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/27/2005
|
Application #:
|
10734439
|
Filing Dt:
|
12/11/2003
|
|
Publication #:
|
|
Pub Dt:
|
06/16/2005
| | | | |
|
Title:
|
IMPRINT SUPPRESSION CIRCUIT SCHEME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/28/2006
|
Application #:
|
10734593
|
Filing Dt:
|
12/15/2003
|
|
Publication #:
|
|
Pub Dt:
|
06/16/2005
| | | | |
|
Title:
|
METHOD FOR REMOVING A RESIST MASK WITH HIGH SELECTIVITY TO A CARBON HARD MASK USED FOR SEMICONDUCTOR STRUCTURING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/15/2005
|
Application #:
|
10738349
|
Filing Dt:
|
12/16/2003
|
|
Publication #:
|
|
Pub Dt:
|
06/16/2005
| | | | |
|
Title:
|
RANDOM ACCESS MEMORY USING PRECHARGE TIMERS IN TEST MODE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/09/2006
|
Application #:
|
10739071
|
Filing Dt:
|
12/19/2003
|
|
Publication #:
|
|
Pub Dt:
|
06/23/2005
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR CONTROLLING REFRESH CYCLES OF A PLURAL CYCLE REFRESH SCHEME IN A DYNAMIC MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/20/2006
|
Application #:
|
10739097
|
Filing Dt:
|
12/19/2003
|
|
Publication #:
|
|
Pub Dt:
|
06/23/2005
| | | | |
|
Title:
|
INPUT BUFFER CIRCUIT INCLUDING REFERENCE VOLTAGE MONITORING CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/17/2006
|
Application #:
|
10739398
|
Filing Dt:
|
12/19/2003
|
|
Publication #:
|
|
Pub Dt:
|
06/23/2005
| | | | |
|
Title:
|
OSCILLATOR WITH TEMPERATURE CONTROL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/21/2006
|
Application #:
|
10740026
|
Filing Dt:
|
12/18/2003
|
|
Publication #:
|
|
Pub Dt:
|
06/23/2005
| | | | |
|
Title:
|
METHODS FOR FORMING VERTICAL GATE TRANSISTORS PROVIDING IMPROVED ISOLATION AND ALIGNMENT OF VERTICAL GATE CONTACTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/10/2005
|
Application #:
|
10744804
|
Filing Dt:
|
12/23/2003
|
|
Title:
|
INPUT BUFFER WITH DIFFERENTIAL AMPLIFIER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/18/2008
|
Application #:
|
10744807
|
Filing Dt:
|
12/23/2003
|
|
Publication #:
|
|
Pub Dt:
|
06/23/2005
| | | | |
|
Title:
|
TEMPERATURE COMPENSATED DELAY SIGNALS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/19/2006
|
Application #:
|
10747277
|
Filing Dt:
|
12/30/2003
|
|
Publication #:
|
|
Pub Dt:
|
06/30/2005
| | | | |
|
Title:
|
BURST MODE IMPLEMENTATION IN A MEMORY DEVICE
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
10748224
|
Filing Dt:
|
12/31/2003
|
|
Publication #:
|
|
Pub Dt:
|
06/30/2005
| | | | |
|
Title:
|
Memory device controlled with user-defined commands
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/22/2005
|
Application #:
|
10757275
|
Filing Dt:
|
01/14/2004
|
|
Title:
|
MEMORY WITH AUTO REFRESH TO DESIGNATED BANKS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/09/2006
|
Application #:
|
10766428
|
Filing Dt:
|
01/28/2004
|
|
Publication #:
|
|
Pub Dt:
|
07/28/2005
| | | | |
|
Title:
|
MEMORY DEVICE WITH NON-VARIABLE WRITE LATENCY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/30/2007
|
Application #:
|
10767928
|
Filing Dt:
|
01/29/2004
|
|
Publication #:
|
|
Pub Dt:
|
08/04/2005
| | | | |
|
Title:
|
METHOD FOR FORMATION OF AN ULTRA-THIN FILM AND SEMICONDUCTOR DEVICE CONTAINING SUCH A FILM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/05/2005
|
Application #:
|
10768202
|
Filing Dt:
|
01/30/2004
|
|
Title:
|
SYSTEM AND METHOD FOR REFRESHING A DYNAMIC MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/09/2006
|
Application #:
|
10795611
|
Filing Dt:
|
03/08/2004
|
|
Publication #:
|
|
Pub Dt:
|
09/08/2005
| | | | |
|
Title:
|
METHOD FOR PRODUCING SEMICONDUCTOR MEMORY DEVICES AND INTEGRATED MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/28/2006
|
Application #:
|
10804840
|
Filing Dt:
|
03/19/2004
|
|
Publication #:
|
|
Pub Dt:
|
09/22/2005
| | | | |
|
Title:
|
CLOCK STOP DETECTOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/03/2006
|
Application #:
|
10805024
|
Filing Dt:
|
03/18/2004
|
|
Publication #:
|
|
Pub Dt:
|
09/22/2005
| | | | |
|
Title:
|
MEMORY DEVICE WITH COMMON ROW INTERFACE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/30/2007
|
Application #:
|
10808190
|
Filing Dt:
|
03/24/2004
|
|
Publication #:
|
|
Pub Dt:
|
09/29/2005
| | | | |
|
Title:
|
TEMPERATURE SENSOR SCHEME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/26/2006
|
Application #:
|
10809826
|
Filing Dt:
|
03/26/2004
|
|
Publication #:
|
|
Pub Dt:
|
09/29/2005
| | | | |
|
Title:
|
CLOCK DISTORTION DETECTOR USING A SYNCHRONOUS MIRROR DELAY CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/19/2008
|
Application #:
|
10812991
|
Filing Dt:
|
03/31/2004
|
|
Publication #:
|
|
Pub Dt:
|
10/06/2005
| | | | |
|
Title:
|
SWITCHING DEVICE FOR CONFIGURABLE INTERCONNECT AND METHOD FOR PREPARING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/06/2005
|
Application #:
|
10815223
|
Filing Dt:
|
03/31/2004
|
|
Publication #:
|
|
Pub Dt:
|
10/13/2005
| | | | |
|
Title:
|
CHARGE-TRAPPING MEMORY CELL ARRAY AND METHOD FOR PRODUCTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/11/2005
|
Application #:
|
10815224
|
Filing Dt:
|
03/31/2004
|
|
Publication #:
|
|
Pub Dt:
|
10/06/2005
| | | | |
|
Title:
|
CIRCUIT BOARD FOR CONNECTING AN INTEGRATED CIRCUIT TO A SUPPORT AND IC BGA PACKAGE USING SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/17/2006
|
Application #:
|
10820292
|
Filing Dt:
|
04/08/2004
|
|
Publication #:
|
|
Pub Dt:
|
10/13/2005
| | | | |
|
Title:
|
MULTICHIP PACKAGE WITH CLOCK FREQUENCY ADJUSTMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/13/2006
|
Application #:
|
10826840
|
Filing Dt:
|
04/16/2004
|
|
Publication #:
|
|
Pub Dt:
|
10/20/2005
| | | | |
|
Title:
|
THRESHOLD VOLTAGE DETECTOR FOR PROCESS EFFECT COMPENSATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/09/2006
|
Application #:
|
10832117
|
Filing Dt:
|
04/26/2004
|
|
Publication #:
|
|
Pub Dt:
|
10/27/2005
| | | | |
|
Title:
|
MEMORY WITH ADJUSTABLE ACCESS TIME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/08/2006
|
Application #:
|
10833927
|
Filing Dt:
|
04/28/2004
|
|
Publication #:
|
|
Pub Dt:
|
11/03/2005
| | | | |
|
Title:
|
CIRCUIT MODULE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/06/2007
|
Application #:
|
10833948
|
Filing Dt:
|
04/28/2004
|
|
Publication #:
|
|
Pub Dt:
|
11/03/2005
| | | | |
|
Title:
|
CIRCUIT BOARD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/06/2005
|
Application #:
|
10834276
|
Filing Dt:
|
04/29/2004
|
|
Publication #:
|
|
Pub Dt:
|
11/03/2005
| | | | |
|
Title:
|
SWITCHING DEVICE FOR RECONFIGURABLE INTERCONNECT AND METHOD FOR MAKING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/08/2006
|
Application #:
|
10835390
|
Filing Dt:
|
04/30/2004
|
|
Publication #:
|
|
Pub Dt:
|
11/03/2005
| | | | |
|
Title:
|
FLASH MEMORY CELL, FLASH MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/04/2006
|
Application #:
|
10835393
|
Filing Dt:
|
04/30/2004
|
|
Publication #:
|
|
Pub Dt:
|
11/03/2005
| | | | |
|
Title:
|
METHOD OF OPTIMIZING THE TIMING BETWEEN SIGNALS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/20/2007
|
Application #:
|
10836753
|
Filing Dt:
|
04/30/2004
|
|
Publication #:
|
|
Pub Dt:
|
11/03/2005
| | | | |
|
Title:
|
PROCESS MONITORING BY COMPARING DELAYS PROPORTIONAL TO TEST VOLTAGES AND REFERENCE VOLTAGES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/28/2006
|
Application #:
|
10836754
|
Filing Dt:
|
04/30/2004
|
|
Publication #:
|
|
Pub Dt:
|
11/03/2005
| | | | |
|
Title:
|
DUTY CYCLE CORRECTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/17/2007
|
Application #:
|
10838535
|
Filing Dt:
|
05/04/2004
|
|
Publication #:
|
|
Pub Dt:
|
11/10/2005
| | | | |
|
Title:
|
METHOD FOR LOCALIZATION AND GENERATION OF SHORT CRITICAL SEQUENCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/31/2006
|
Application #:
|
10854463
|
Filing Dt:
|
05/26/2004
|
|
Publication #:
|
|
Pub Dt:
|
12/01/2005
| | | | |
|
Title:
|
CHIP TO CHIP INTERFACE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/2008
|
Application #:
|
10855946
|
Filing Dt:
|
05/28/2004
|
|
Publication #:
|
|
Pub Dt:
|
12/01/2005
| | | | |
|
Title:
|
METHOD FOR INITIALIZING THE COMPUTATION OF A QUASI-PERIODIC STEADY STATE OF A MULTI-TONE SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/30/2006
|
Application #:
|
10863516
|
Filing Dt:
|
06/09/2004
|
|
Publication #:
|
|
Pub Dt:
|
12/15/2005
| | | | |
|
Title:
|
COMPARATOR AND METHOD FOR AMPLIFYING AN INPUT SIGNAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/20/2007
|
Application #:
|
10867896
|
Filing Dt:
|
06/15/2004
|
|
Publication #:
|
|
Pub Dt:
|
12/15/2005
| | | | |
|
Title:
|
COMPARATOR USING DIFFERENTIAL AMPLIFIER WITH REDUCED CURRENT CONSUMPTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/20/2007
|
Application #:
|
10870100
|
Filing Dt:
|
06/17/2004
|
|
Publication #:
|
|
Pub Dt:
|
12/22/2005
| | | | |
|
Title:
|
INPUT RETURN PATH BASED ON VDDQ/VSSQ
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/04/2006
|
Application #:
|
10877299
|
Filing Dt:
|
06/25/2004
|
|
Publication #:
|
|
Pub Dt:
|
12/29/2005
| | | | |
|
Title:
|
WAFER PROBECARD INTERFACE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/12/2008
|
Application #:
|
10877649
|
Filing Dt:
|
06/25/2004
|
|
Publication #:
|
|
Pub Dt:
|
12/29/2005
| | | | |
|
Title:
|
TEST CIRCUITRY WAFER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2007
|
Application #:
|
10881338
|
Filing Dt:
|
06/30/2004
|
|
Publication #:
|
|
Pub Dt:
|
01/05/2006
| | | | |
|
Title:
|
PROCESS FOR FABRICATION OF A FERROCAPACITOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/06/2006
|
Application #:
|
10889670
|
Filing Dt:
|
07/13/2004
|
|
Publication #:
|
|
Pub Dt:
|
01/27/2005
| | | | |
|
Title:
|
METHOD FOR FABRICATING A TRENCH CAPACITOR WITH AN INSULATION COLLAR WHICH IS ELECTRICALLY CONNECTED TO A SUBSTRATE ON ONE SIDE VIA A BURIED CONTACT, IN PARTICULAR FOR A SEMICONDUCTOR MEMORY CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/21/2007
|
Application #:
|
10891051
|
Filing Dt:
|
07/15/2004
|
|
Publication #:
|
|
Pub Dt:
|
01/19/2006
| | | | |
|
Title:
|
METHOD FOR FORMING A CAPACITOR FOR AN INTEGRATED CIRCUIT AND INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/10/2006
|
Application #:
|
10916013
|
Filing Dt:
|
08/11/2004
|
|
Publication #:
|
|
Pub Dt:
|
03/31/2005
| | | | |
|
Title:
|
MEMORY CELL WITH NANOCRYSTALS OR NANODOTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/05/2007
|
Application #:
|
10917176
|
Filing Dt:
|
08/12/2004
|
|
Publication #:
|
|
Pub Dt:
|
02/24/2005
| | | | |
|
Title:
|
APPARATUS AND METHOD FOR TESTING CIRCUIT UNITS TO BE TESTED
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/08/2006
|
Application #:
|
10922005
|
Filing Dt:
|
08/19/2004
|
|
Publication #:
|
|
Pub Dt:
|
03/31/2005
| | | | |
|
Title:
|
TEST ARRANGEMENT FOR TESTING SEMICONDUCTOR CIRCUIT CHIPS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/18/2006
|
Application #:
|
10927312
|
Filing Dt:
|
08/27/2004
|
|
Publication #:
|
|
Pub Dt:
|
03/03/2005
| | | | |
|
Title:
|
SEMICONDUCTOR MEMORY MODULE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/04/2006
|
Application #:
|
10927952
|
Filing Dt:
|
08/27/2004
|
|
Publication #:
|
|
Pub Dt:
|
05/12/2005
| | | | |
|
Title:
|
FBGA ARRANGEMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/21/2006
|
Application #:
|
10934114
|
Filing Dt:
|
09/03/2004
|
|
Publication #:
|
|
Pub Dt:
|
05/05/2005
| | | | |
|
Title:
|
PROCESS FOR SEALING PLASMA-DAMAGED, POROUS LOW-K MATERIALS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/11/2006
|
Application #:
|
10935520
|
Filing Dt:
|
09/07/2004
|
|
Publication #:
|
|
Pub Dt:
|
03/31/2005
| | | | |
|
Title:
|
METHOD FOR FABRICATING A TRENCH CAPACITOR HAVING AN INSULATION COLLAR, WHICH IS ELECTRICALLY CONNECTED TO A SUBSTRATE ON ONE SIDE VIA A BURIED CONTACT, IN PARTICULAR FOR A SEMICONDUCTOR MEMORY CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/03/2006
|
Application #:
|
10937903
|
Filing Dt:
|
09/10/2004
|
|
Publication #:
|
|
Pub Dt:
|
04/07/2005
| | | | |
|
Title:
|
METHOD FOR FABRICATING AN INTEGRATED CIRCUIT DEVICE WITH THROUGH-PLATING ELEMENTS AND TERMINAL UNITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/01/2008
|
Application #:
|
10941706
|
Filing Dt:
|
09/15/2004
|
|
Publication #:
|
|
Pub Dt:
|
04/07/2005
| | | | |
|
Title:
|
DATA PROCESSING CIRCUIT APPARATUS HAVING A DATA TRANSMISSION UNIT OF REDUNDANT DESIGN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/02/2006
|
Application #:
|
10946660
|
Filing Dt:
|
09/22/2004
|
|
Publication #:
|
|
Pub Dt:
|
04/07/2005
| | | | |
|
Title:
|
METHOD FOR TESTING CIRCUIT UNITS TO BE TESTED AND TEST APPARATUS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/27/2005
|
Application #:
|
10947449
|
Filing Dt:
|
09/23/2004
|
|
Publication #:
|
|
Pub Dt:
|
03/31/2005
| | | | |
|
Title:
|
CIRCUIT ARRANGEMENT FOR SETTING A VOLTAGE SUPPLY FOR A TEST MODE OF AN INTEGRATED MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/18/2007
|
Application #:
|
10948570
|
Filing Dt:
|
09/24/2004
|
|
Publication #:
|
|
Pub Dt:
|
05/19/2005
| | | | |
|
Title:
|
METHOD FOR CARRYING OUT A DOUBLE OR MULTIPLE EXPOSURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/08/2008
|
Application #:
|
10948741
|
Filing Dt:
|
09/24/2004
|
|
Publication #:
|
|
Pub Dt:
|
05/05/2005
| | | | |
|
Title:
|
SIGNAL TEST PROCEDURE FOR TESTING SEMI-CONDUCTOR COMPONENTS AND A TEST APPARATUS FOR TESTING SEMI-CONDUCTOR COMPONENTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/21/2006
|
Application #:
|
10949793
|
Filing Dt:
|
09/24/2004
|
|
Publication #:
|
|
Pub Dt:
|
05/05/2005
| | | | |
|
Title:
|
APPARATUS FOR CALIBRATING THE RELATIVE PHASE OF TWO RECEPTION SIGNALS OF A MEMORY CHIP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/17/2007
|
Application #:
|
10949935
|
Filing Dt:
|
09/24/2004
|
|
Publication #:
|
|
Pub Dt:
|
06/23/2005
| | | | |
|
Title:
|
APPARATUS FOR TESTING A MEMORY MODULE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/01/2006
|
Application #:
|
10950477
|
Filing Dt:
|
09/28/2004
|
|
Publication #:
|
|
Pub Dt:
|
03/31/2005
| | | | |
|
Title:
|
NONVOLATILE INTEGRATED SEMICONDUCTOR MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/17/2007
|
Application #:
|
10951596
|
Filing Dt:
|
09/29/2004
|
|
Publication #:
|
|
Pub Dt:
|
03/31/2005
| | | | |
|
Title:
|
ALIGNMENT MARK FOR COARSE ALIGNMENT AND FINE ALIGNMENT OF A SEMICONDUCTOR WAFER IN AN EXPOSURE TOOL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/22/2008
|
Application #:
|
10951805
|
Filing Dt:
|
09/29/2004
|
|
Publication #:
|
|
Pub Dt:
|
04/21/2005
| | | | |
|
Title:
|
PHASE SHIFT MASK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/25/2006
|
Application #:
|
10952371
|
Filing Dt:
|
09/29/2004
|
|
Publication #:
|
|
Pub Dt:
|
05/05/2005
| | | | |
|
Title:
|
METHOD FOR FABRICATING MEMORY CELLS AND MEMORY CELL ARRAY
|
|
