Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 024055/0581 | |
| Pages: | 3 |
| | Recorded: | 03/10/2010 | | |
| Attorney Dkt #: | 050429-0010 |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
11
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Patent #:
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Issue Dt:
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12/23/1997
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Application #:
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08559746
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Filing Dt:
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11/15/1995
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Title:
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DATA OUTPUT CIRCUIT WITH REDUCED OUTPUT NOISE
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Patent #:
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Issue Dt:
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02/27/2001
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Application #:
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09095612
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Filing Dt:
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06/11/1998
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Title:
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SEMICONDUCTOR DEVICE COMPRISING CAPACITOR AND METHOD OF FABRICATING THE SAME
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Patent #:
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Issue Dt:
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12/19/2000
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Application #:
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09298968
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Filing Dt:
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04/26/1999
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Title:
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DATA OUTPUT CIRCUIT WITH REDUCED OUTPUT NOISE
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Patent #:
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Issue Dt:
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10/01/2002
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Application #:
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09521468
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Filing Dt:
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03/08/2000
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Title:
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SEMICONDUCTOR DEVICE HAVING A CHIP, REINFORCING PLATE, AND SEALING MATERIAL SHARING A COMMON REAR SURFACE
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Patent #:
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Issue Dt:
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02/18/2003
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Application #:
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09685896
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Filing Dt:
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10/11/2000
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING THE SAME
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Patent #:
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Issue Dt:
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09/03/2002
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Application #:
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09708509
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Filing Dt:
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11/09/2000
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Title:
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DATA OUTPUT CIRCUIT WITH REDUCED OUTPUT NOISE
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Patent #:
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Issue Dt:
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10/21/2003
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Application #:
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09776681
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Filing Dt:
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02/06/2001
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Publication #:
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Pub Dt:
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01/24/2002
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Title:
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SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE OPERATING WITH LOW POWER CONSUMPTION
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Patent #:
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Issue Dt:
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08/19/2003
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Application #:
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09832025
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Filing Dt:
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04/11/2001
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Publication #:
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Pub Dt:
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05/16/2002
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Title:
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THIN FILM MAGNETIC MEMORY DEVICE HAVING A HIGHLY INTEGRATED MEMORY ARRAY
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Patent #:
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Issue Dt:
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02/19/2002
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Application #:
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09852087
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Filing Dt:
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05/10/2001
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Title:
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Thin film magnetic memory device including memory cells having a magnetic tunnel junction
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Patent #:
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Issue Dt:
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03/04/2003
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Application #:
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09900917
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Filing Dt:
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07/10/2001
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Publication #:
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Pub Dt:
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06/06/2002
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Title:
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SEMICONDUCTOR MEMORY
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Patent #:
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Issue Dt:
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08/12/2003
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Application #:
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09920624
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Filing Dt:
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08/03/2001
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Title:
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DATA OUTPUT CIRCUIT WITH REDUCED OUTPUT NOISE
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Assignee
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| 6-2, OTEMACHI 2-CHOME |
| CHIYODA-KU, TOKYO, JAPAN 100-0004 |
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Correspondence name and address
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STEPHEN A. BECKER
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555 THIRTEENTH STREET, NW
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WASHINGTON, DC 20005
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