skip navigationU S P T O SealUnited States Patent and Trademark Office AOTW logo
Home|Site Index|Search|Guides|Contacts|eBusiness|eBiz alerts|News|Help
Assignments on the Web > Patent Query
Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:024088/0280   Pages: 3
Recorded: 03/16/2010
Attorney Dkt #:CSMPTE TO GLOBALFOUNDRIES
Conveyance: CHANGE OF NAME (SEE DOCUMENT FOR DETAILS).
Total properties: 10
1
Patent #:
Issue Dt:
08/14/2012
Application #:
12422694
Filing Dt:
04/13/2009
Publication #:
Pub Dt:
10/14/2010
Title:
INTEGRATED CIRCUIT SYSTEM WITH A FLOATING DIELECTRIC REGION AND METHOD OF MANUFACTURE THEREOF
2
Patent #:
Issue Dt:
02/22/2011
Application #:
12429916
Filing Dt:
04/24/2009
Publication #:
Pub Dt:
10/28/2010
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM AND METHOD OF MANUFACTURE THEREOF
3
Patent #:
Issue Dt:
02/04/2014
Application #:
12432162
Filing Dt:
04/29/2009
Publication #:
Pub Dt:
11/04/2010
Title:
INTEGRATED CIRCUIT COMMUNICATION SYSTEM WITH DIFFERENTIAL SIGNAL AND METHOD OF MANUFACTURE THEREOF
4
Patent #:
Issue Dt:
04/02/2013
Application #:
12465431
Filing Dt:
05/13/2009
Publication #:
Pub Dt:
11/18/2010
Title:
MASK SYSTEM EMPLOYING SUBSTANTIALLY CIRCULAR OPTICAL PROXIMITY CORRECTION TARGET AND METHOD OF MANUFACTURE THEREOF
5
Patent #:
Issue Dt:
06/14/2011
Application #:
12470028
Filing Dt:
05/21/2009
Publication #:
Pub Dt:
11/25/2010
Title:
METHOD OF MANUFACTURE AN INTEGRATED CIRCUIT SYSTEM WITH THROUGH SILICON VIA
6
Patent #:
NONE
Issue Dt:
Application #:
12471803
Filing Dt:
05/26/2009
Publication #:
Pub Dt:
12/02/2010
Title:
INTEGRATED CIRCUIT SYSTEM WITH VERTICAL CONTROL GATE AND METHOD OF MANUFACTURE THEREOF
7
Patent #:
Issue Dt:
03/20/2012
Application #:
12488451
Filing Dt:
06/19/2009
Publication #:
Pub Dt:
12/23/2010
Title:
INTEGRATED CIRCUIT SYSTEM WITH HIGH VOLTAGE TRANSISTOR AND METHOD OF MANUFACTURE THEREOF
8
Patent #:
Issue Dt:
10/09/2012
Application #:
12541373
Filing Dt:
08/14/2009
Publication #:
Pub Dt:
02/17/2011
Title:
INTEGRATED CIRCUIT SYSTEM WITH SEALRING AND METHOD OF MANUFACTURE THEREOF
9
Patent #:
Issue Dt:
10/13/2015
Application #:
12544747
Filing Dt:
08/20/2009
Publication #:
Pub Dt:
02/24/2011
Title:
INTEGRATED CIRCUIT SYSTEM WITH BAND TO BAND TUNNELING AND METHOD OF MANUFACTURE THEREOF
10
Patent #:
Issue Dt:
12/10/2013
Application #:
12613224
Filing Dt:
11/05/2009
Publication #:
Pub Dt:
05/05/2011
Title:
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CORE REGION AND BOND PAD AND METHOD OF MANUFACTURE THEREOF
Assignor
1
Exec Dt:
01/15/2010
Assignee
1
60 WOODLANDS INDUSTRIAL PARK D
STREET 2
SINGAPORE 738406, SINGAPORE
Correspondence name and address
MIKIO ISHIMARU
LAW OFFICES OF MIKIO ISHIMARU
333 W. EL CAMINO REAL, SUITE # 330
SUNNYVALE, CA 94087

Search Results as of: 05/08/2024 05:54 PM
If you have any comments or questions concerning the data displayed, contact PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified: August 25, 2017 v.2.6
| .HOME | INDEX| SEARCH | eBUSINESS | CONTACT US | PRIVACY STATEMENT