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Patent #:
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Issue Dt:
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10/10/2000
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Application #:
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09010081
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Filing Dt:
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01/21/1998
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Title:
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INSITU DOPED METAL POLICIDE
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Patent #:
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Issue Dt:
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05/02/2000
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Application #:
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09014431
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Filing Dt:
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01/27/1998
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Title:
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LOW TEMPERATURE REFLOW DIELECTRIC-FLUORINATED BPSG
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Patent #:
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Issue Dt:
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05/23/2000
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Application #:
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09014805
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Filing Dt:
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01/28/1998
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Title:
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HIGH SELECTIVITY COLLAR OXIDE ETCH PROCESSES
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Patent #:
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Issue Dt:
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10/19/1999
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Application #:
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09017019
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Filing Dt:
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02/02/1998
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Title:
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REPAIRABLE SEMICONDUCTOR INTEGRATED CIRCUIT MEMORY BY SELECTIVE ASSIGNMENT OF GROUPS OF REDUNDANCY ELEMENTS TO DOMAINS `
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Patent #:
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Issue Dt:
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12/28/1999
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Application #:
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09031995
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Filing Dt:
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02/27/1998
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Title:
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METHOD FOR FORMING TRENCH CAPACITORS IN AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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07/25/2000
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Application #:
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09034519
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Filing Dt:
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03/04/1998
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Title:
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MEMORY CELL STRUCTURE AND FABRICATION
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Patent #:
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Issue Dt:
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11/07/2000
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Application #:
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09036319
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Filing Dt:
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03/06/1998
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Title:
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SIGNALING IMPROVEMENT USING EXTENDED TRANSMISSION LINES ON HIGH SPEED DIMMS
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Patent #:
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Issue Dt:
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02/01/2000
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Application #:
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09036478
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Filing Dt:
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03/06/1998
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Title:
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METHODS AND APPARATUS FOR CHEMICAL MECHANICAL PLANARIZATION (CMP) OF A SEMICONDUCTOR WAFER
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Patent #:
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Issue Dt:
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03/02/2004
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Application #:
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09037287
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Filing Dt:
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03/09/1998
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Title:
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SELF ALIGNED BURIED PLATE
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Patent #:
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Issue Dt:
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01/09/2001
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Application #:
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09047581
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Filing Dt:
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03/25/1998
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Title:
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SEMICONDUCTOR DEVICE WITH VERTICAL TRANSISTOR AND BURIED WORD LINE
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Patent #:
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Issue Dt:
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06/27/2000
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Application #:
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09052683
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Filing Dt:
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03/31/1998
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Title:
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IMPROVED CONTROLLABILITY OF A BURIED DEVICE LAYER
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Patent #:
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Issue Dt:
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06/01/1999
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Application #:
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09052799
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Filing Dt:
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03/31/1998
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Title:
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DYNAMIC RANDOM ACCESS MEMORY CIRCUIT AND METHODS THEREFOR
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Patent #:
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Issue Dt:
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07/24/2001
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Application #:
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09056119
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Filing Dt:
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04/06/1998
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Title:
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TRENCH CAPACITOR WITH EPI BURIED LAYER
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Patent #:
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Issue Dt:
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11/09/1999
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Application #:
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09061565
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Filing Dt:
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04/16/1998
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Title:
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REMOVAL OF POST-RIE POLYMER ON A1/CU METAL LINE
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Patent #:
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Issue Dt:
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04/04/2000
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Application #:
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09074882
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Filing Dt:
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05/08/1998
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Title:
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METHOD OF FORMING STACK CAPACITOR WITH IMPROVED PLUG CONDUCTIVITY
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Patent #:
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Issue Dt:
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03/21/2000
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Application #:
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09093796
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Filing Dt:
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06/09/1998
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Title:
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SEMICONDUCTORS HAVING DEFECT DENUDED ZONES
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Patent #:
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Issue Dt:
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08/15/2000
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Application #:
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09093801
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Filing Dt:
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06/09/1998
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Title:
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METHOD OF FORMING DEEP TRENCH CAPACITORS
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Patent #:
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Issue Dt:
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08/08/2000
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Application #:
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09093802
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Filing Dt:
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06/09/1998
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Title:
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CLOCK LATENCY COMPENSATION CIRCUIT FOR DDR TIMING
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Patent #:
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Issue Dt:
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07/18/2000
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Application #:
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09095793
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Filing Dt:
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06/11/1998
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Title:
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VERTICAL DEVICE FORMED ADJACENT TO A WORLDLINE SIDEWALL AND METHOD FOR SEMICONDUCTOR CHIPS
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Patent #:
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Issue Dt:
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08/03/1999
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Application #:
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09097545
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Filing Dt:
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06/15/1998
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Title:
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MEMORY WITH REDUCED WIRE CONNECTIONS
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Patent #:
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Issue Dt:
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10/30/2001
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Application #:
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09097783
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Filing Dt:
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06/15/1998
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Title:
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TRENCH CAPACITOR WITH ISOLATION COLLAR AND CORRESPONDING MANUFACTURING METHOD
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Patent #:
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Issue Dt:
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11/21/2000
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Application #:
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09097784
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Filing Dt:
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06/15/1998
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Title:
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OVERLAY MEASUREMENT TECHNIQUE USING MOIRE PATTERNS
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Patent #:
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Issue Dt:
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05/09/2000
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Application #:
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09097872
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Filing Dt:
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06/15/1998
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Title:
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HIGH DENSITY PLASMA CVD PROCESS FOR MAKING DIELECTRIC ANTI-REFLECTIVE COATINGS
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Patent #:
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Issue Dt:
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06/13/2000
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Application #:
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09098203
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Filing Dt:
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06/16/1998
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Title:
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A METHOD FOR FORMING ELECTRICAL ISOLATION FOR SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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03/28/2000
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Application #:
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09098785
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Filing Dt:
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06/17/1998
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Title:
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PHASE SHIFT MASK HAVING MULTIPLE ALIGNMENT INDICATIONS AND METHOD OF MANUFACTURE
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Patent #:
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Issue Dt:
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10/24/2000
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Application #:
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09099093
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Filing Dt:
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06/17/1998
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Title:
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SEMICONDUCTOR METALIZATION SYSTEM AND METHOD BACKGROUND OF THE INVENTION
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Patent #:
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Issue Dt:
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02/27/2001
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Application #:
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09102471
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Filing Dt:
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06/22/1998
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Title:
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LOW-RESISTANCE SALICIDE FILL FOR TRENCH CAPACITORS
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Patent #:
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Issue Dt:
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03/28/2000
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Application #:
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09103871
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Filing Dt:
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06/24/1998
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Title:
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LOCK ARRANGEMENT FOR A CALABRATED DDL IN DDR SDRAM APPLICATIONS
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Patent #:
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Issue Dt:
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07/17/2001
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Application #:
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09105107
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Filing Dt:
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06/24/1998
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Title:
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METHOD FOR FORMING A SEMINCONDUCTOR FUSE
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Patent #:
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Issue Dt:
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12/26/2000
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Application #:
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09105226
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Filing Dt:
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06/25/1998
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Title:
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SELF-ALIGNED FORMATION AND METHOD FOR SEMICONDUCTORS
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Patent #:
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Issue Dt:
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01/25/2000
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Application #:
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09105580
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Filing Dt:
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06/26/1998
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Title:
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BOTTLE-SHAPED TRENCH CAPACITOR WITH EPI BURIED LAYER
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Patent #:
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Issue Dt:
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12/26/2000
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Application #:
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09105632
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Filing Dt:
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06/26/1998
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Title:
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SYSTEM AND METHOD FOR OPTICALLY MEASURING DIELECTRIC THICKNESS IN SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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10/15/2002
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Application #:
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09105633
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Filing Dt:
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06/26/1998
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Title:
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LOW LEAKAGE, LOW CAPACITANCE ISOLATION MATERIAL
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Patent #:
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Issue Dt:
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03/14/2000
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Application #:
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09105647
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Filing Dt:
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06/26/1998
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Title:
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SEMICONDUCTOR STRUCTURE INCLUDING A CONDUCTIVE FUSE AND PROCESS FOR FABRICATION THEREOF
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Patent #:
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Issue Dt:
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08/31/1999
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Application #:
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09105945
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Filing Dt:
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06/26/1998
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Title:
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TRENCH CAPACITOR WITH EPI BURIED LAYER
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Patent #:
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Issue Dt:
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04/11/2000
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Application #:
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09107191
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Filing Dt:
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06/29/1998
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Title:
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INTERLEAVED SENSE AMPLIFIER WITH A SINGLE-SIDED PRECHARGE DEVICE
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Patent #:
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Issue Dt:
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09/19/2000
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Application #:
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09107672
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Filing Dt:
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06/30/1998
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Title:
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SEMICONDUCTOR MANUFACTURING METHOD
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Patent #:
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Issue Dt:
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11/20/2001
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Application #:
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09107980
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Filing Dt:
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06/30/1998
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Title:
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METHOD FOR FORMING A HIGH SURFACE AREA TRENCH CAPACITOR
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Patent #:
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Issue Dt:
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12/26/2000
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Application #:
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09123298
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Filing Dt:
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07/28/1998
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Title:
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TAPERED ELECTRODE FOR STACKED CAPACITORS
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Patent #:
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Issue Dt:
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06/13/2000
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Application #:
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09127262
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Filing Dt:
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07/31/1998
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Title:
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APPARATUS AND METHOD FOR FORMING CONTROLLED DEEP TRENCH TOP ISOLATION LAYERS
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Patent #:
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Issue Dt:
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05/23/2000
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Application #:
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09127740
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Filing Dt:
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08/03/1998
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Title:
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TIMING OF WORLDLINE ACTIVATION FOR DC BURN-IN OF A DRAM WITH THE SELF-REFRESH
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Patent #:
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Issue Dt:
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02/11/2003
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Application #:
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09130226
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Filing Dt:
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08/06/1998
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Title:
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METHODS TO CONTROL THE THRESHOLD VOLTAGE OF A DEEP TRENCH CORNER DEVICE
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Patent #:
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Issue Dt:
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08/01/2000
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Application #:
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09130324
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08/06/1998
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Title:
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A METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURES INCLUDING A PAIR OF MOSFETS
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Issue Dt:
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01/23/2001
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09133203
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Filing Dt:
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08/13/1998
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Title:
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INTEGRATION SCHEME ENHANCING DEEP TRENCH CAPACITANCE IN SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES
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Patent #:
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10/26/1999
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09135866
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Filing Dt:
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08/18/1998
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Title:
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A CMP PROCESS USING INDICATOR AREAS TO DETERMINE ENDPOINT
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Patent #:
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Issue Dt:
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08/29/2000
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09136604
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Filing Dt:
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08/19/1998
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Title:
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METHOD FOR MAKING DRAM CAPACITOR STRAP
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Patent #:
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Issue Dt:
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05/22/2001
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09139514
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Filing Dt:
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08/25/1998
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Title:
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WORDLINE DRIVER CIRCUIT USING RING-SHAPED DEVICES
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Issue Dt:
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01/09/2001
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Application #:
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09144297
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Filing Dt:
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08/31/1998
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Title:
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RECOVERY OF ELECTRONIC PROPERTIES IN PROCESS-DAMAGED FERROELECTRICS BY VOLTAGE-CYCLING
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Patent #:
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Issue Dt:
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08/20/2002
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Application #:
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09146870
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Filing Dt:
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09/03/1998
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Title:
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COMBINED PREANNEAL/OXIDATION STEP USING RAPID THERMAL PROCESSING
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Patent #:
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Issue Dt:
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11/21/2000
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Application #:
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09156071
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Filing Dt:
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09/17/1998
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Title:
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COMPOSITION AND METHOD FOR REDUCING DISHING IN PATTERNED METAL DURING CMP PROCESS
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Issue Dt:
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10/17/2000
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09161793
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09/28/1998
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Title:
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METHOD OF ENHANCING SEMICONDUCTOR WAFER RELEASE
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Issue Dt:
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10/24/2000
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09161861
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09/28/1998
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Title:
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STACKED CAPACITATOR MEMORY CELL AND METHOD OF FABRICATION
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03/27/2001
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09162867
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09/29/1998
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Title:
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MEMORY CELL WITH A STACKED CAPACITOR
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02/13/2001
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09163670
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Filing Dt:
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09/30/1998
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Title:
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6 1/4 F2 DRAM CELL STRUCTURE WITH FOUR NODES PER BITLINE-STUD AND TWO TOPOLOGICAL WORDLINE LEVELS
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11/27/2001
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09175267
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10/20/1998
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METHOD FOR FABRICATING TRANSISTORS
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10/03/2000
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09181964
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10/29/1998
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DEEP DIVOT MASK FOR ENHANCED BURIED-CHANNEL PFET PERFORMANCE AND RELIABILITY
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09/19/2000
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09186515
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11/05/1998
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FUSE LAYOUT FOR IMPROVED FUSE BLOW PROCESS WINDOW
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10/31/2000
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09192698
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11/16/1998
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IN-SITU MEASUREMENT METHOD AND APPARATUS FOR SEMICONDUCTOR PROCESSING
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12/05/2000
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09193203
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11/17/1998
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METHOD OF FORMING A TRENCH CAPACITOR USING A RUTILE DIELECTRIC MATERIAL
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10/24/2000
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09200338
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11/25/1998
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DELAY LOCK LOOP
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07/24/2001
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09201205
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11/30/1998
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SLOTTED DAMASCENE LINES FOR LOW RESISTIVE WIRING LINES FOR INTEGRATED CIRCUIT
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02/01/2005
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09204706
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12/03/1998
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07/05/2001
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Title:
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REMOVAL OF POST-RIE POLYMER ON A1/CU METAL LINE
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04/24/2001
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09209198
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12/10/1998
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EXTENDED TRENCH FOR PREVENTING INTERACTION BETWEEN COMPONENTS OF STACKED CAPACITORS
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01/25/2000
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09209199
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12/10/1998
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DISTRIBUTED BLOCK REDUNDANCY FOR MEMORY DEVICES
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05/23/2000
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09209413
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12/10/1998
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METHOD AND APPARATUS FOR PREVENTING FORMATION OF BLACK SILICON ON EDGES OF WAFERS
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10/24/2000
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09213469
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12/17/1998
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Title:
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METHODS FOR ENHANCING THE METAL REMOVAL RATE DURING THE CHEMICAL-MECHANICAL POLISHING PROCESS OF A SEMICONDUCTOR
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04/18/2000
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09218561
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12/22/1998
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Title:
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A REPAIRABLE SEMICONDUCTOR MEMORY CIRCUIT HAVING PARALLEL REDUNDANCY REPLACEMENT WHEREIN REDUNDANCY ELEMENTS REPLACE FAILED ELEMENTS
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04/02/2002
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09228178
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01/11/1999
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03/14/2002
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Title:
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SYSTEM AND METHOD FOR DETERMINING YIELD IMPACT FOR SEMICONDUCTOR DEVICES
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04/24/2001
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09234341
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01/20/1999
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METHOD OF MAKING A MICROELECTRONIC STRUCTURE
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05/16/2000
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09299364
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04/26/1999
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RADIATION-SENSITIVE MIXTURE AND ITS USE
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10/25/2005
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09313424
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Filing Dt:
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05/17/1999
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Title:
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SOI SEMICONDUCTOR CONFIGURATION AND METHOD OF FABRICATING THE SAME
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Patent #:
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Issue Dt:
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07/24/2001
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Application #:
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09317662
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Filing Dt:
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05/24/1999
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Title:
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MEMORY CELL STRUCTURE AND FABRICATION
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Patent #:
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Issue Dt:
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04/30/2002
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Application #:
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09333228
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Filing Dt:
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06/14/1999
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Publication #:
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Pub Dt:
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11/29/2001
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Title:
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IMPROVED METHODS AND APPARATUS FOR CHEMICAL MECHANICAL PLANARIZATION (CMP) OF A SEMICONDUCTOR WAFER
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Patent #:
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Issue Dt:
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03/06/2001
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Application #:
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09390496
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Filing Dt:
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09/03/1999
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Title:
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METHOD FOR THE FABRICATION OF A DOPED SILICON LAYER
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Patent #:
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Issue Dt:
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09/26/2000
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Application #:
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09391717
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Filing Dt:
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09/08/1999
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Title:
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INTEGRATED SEMICONDUCTOR MEMORY
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Patent #:
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Issue Dt:
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01/08/2002
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Application #:
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09391720
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Filing Dt:
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09/08/1999
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Title:
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LAYER CONFIGURATION WITH A MATERIAL LAYER AND A DIFFUSION BARRIER WHICH BLOCKS DIFFUSING MATERIAL COMPONENTS AND PROCESS FOR PRODUCING A DIFFUSION BARRIER
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Patent #:
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Issue Dt:
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03/12/2002
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Application #:
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09394196
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Filing Dt:
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09/10/1999
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Title:
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ELECTRONIC CIRCUIT CONFIGURATION
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Patent #:
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Issue Dt:
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05/08/2001
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Application #:
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09395005
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Filing Dt:
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09/13/1999
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Title:
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INTEGRATED CIRCUIT WITH TWO OPERATING STATES
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Patent #:
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Issue Dt:
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03/13/2001
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Application #:
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09395226
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Filing Dt:
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09/13/1999
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Title:
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PRODUCTION METHOD FOR A TRENCH CAPACITOR WITH AN INSULATION COLLAR
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Patent #:
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Issue Dt:
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07/10/2001
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Application #:
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09395316
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Filing Dt:
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09/13/1999
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Title:
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CAPACITOR WITH HIGH-E DIELECTRIC OR FERROELECTRIC MATERIAL BASED ON THE FIN STACK PRINCIPLE AND PRODUCTION PROCESS USING A NEGATIVE MOLD
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Patent #:
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Issue Dt:
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01/30/2001
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Application #:
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09398695
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Filing Dt:
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09/20/1999
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Title:
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INTEGRATED CIRCUIT MEMORY HAVING A SENSE AMPLIFIER ACTIVATED BASED ON WORD LINE POTENTIALS
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Patent #:
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Issue Dt:
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11/20/2001
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Application #:
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09401387
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Filing Dt:
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09/22/1999
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Title:
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METHOD FOR DETERMINING THE DRIVE CAPABILITY OF A DRIVER CIRCUIT OF AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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01/23/2001
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Application #:
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09401388
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Filing Dt:
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09/22/1999
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Title:
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INTEGRATED MEMORY HAVING A SELF-REPAIR FUNCTION
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Patent #:
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Issue Dt:
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07/31/2001
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Application #:
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09401390
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Filing Dt:
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09/22/1999
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Title:
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BURN-IN TEST DEVICE
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Patent #:
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Issue Dt:
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07/23/2002
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Application #:
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09404494
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Filing Dt:
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09/23/1999
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Title:
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TRENCH CAPACITOR WITH INSULATION COLLAR AND CORRESPONDING FABRICATION METHOD
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Patent #:
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Issue Dt:
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08/14/2001
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Application #:
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09405916
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Filing Dt:
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09/24/1999
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Title:
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MEMORY CELL CONFIGURATION AND PRODUCTION PROCESS THEREFOR
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Patent #:
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Issue Dt:
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06/12/2001
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Application #:
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09407263
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Filing Dt:
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09/27/1999
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Title:
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METHOD FOR FABRICATING A SEMICONDUCTOR STRUCTURE
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Patent #:
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Issue Dt:
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02/13/2001
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Application #:
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09408476
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Filing Dt:
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09/28/1999
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Title:
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INTEGRATED CIRCUIT HAVING A CONTACT-MAKING POINT FOR SELECTING AN OPERATING MODE OF THE INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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07/18/2000
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Application #:
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09408479
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Filing Dt:
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09/28/1999
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Title:
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FERROELECTRIC MEMORY AND METHOD FOR PREVENTING AGING IN A MEMORY CELL
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Patent #:
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Issue Dt:
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12/12/2000
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Application #:
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09408677
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Filing Dt:
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09/30/1999
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Title:
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INTEGRATED CIRCUIT WITH A CONFIGURATION ASSEMBLY
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Patent #:
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Issue Dt:
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02/20/2001
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Application #:
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09408685
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Filing Dt:
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09/30/1999
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Title:
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INTEGRATED CIRCUIT HAVING ADJUSTABLE DELAY UNITS FOR CLOCK SIGNALS
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Patent #:
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Issue Dt:
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02/27/2001
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Application #:
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09408687
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Filing Dt:
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09/30/1999
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Title:
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INTEGRATED CIRCUIT WITH ADJUSTABLE DELAY UNIT
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Patent #:
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Issue Dt:
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04/06/2004
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Application #:
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09408688
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Filing Dt:
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09/30/1999
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Title:
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VERTICAL FIELD EFFECT TRANSISTOR WITH INTERNAL ANNULAR GATE AND METHOD OF PRODUCTION
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Patent #:
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Issue Dt:
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06/12/2001
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Application #:
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09408689
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Filing Dt:
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09/30/1999
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Title:
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CIRCUIT FOR GENERATING OUTPUT SIGNALS AS A FUNCTION OF INPUT SIGNALS
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Patent #:
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Issue Dt:
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02/11/2003
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Application #:
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09423864
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Filing Dt:
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11/15/1999
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Title:
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INTEGRATED CMOS CIRCUIT CONFIGURATION, AND PRODUCTION OF SAME
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Patent #:
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Issue Dt:
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09/25/2001
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Application #:
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09426420
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Filing Dt:
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10/25/1999
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Title:
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IMPLANTATION MASK FOR PRODUCING A MEMORY CELL CONFIGURATION
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Patent #:
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Issue Dt:
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02/20/2001
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Application #:
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09428181
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Filing Dt:
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10/27/1999
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Title:
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METHOD FOR FABRICATING A CAPACITOR
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Patent #:
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Issue Dt:
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03/25/2003
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Application #:
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09431529
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Filing Dt:
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11/01/1999
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Title:
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READ/WRITE MEMORY WITH SELF-TEST DEVICE AND ASSOCIATED TEST METHOD
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Patent #:
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Issue Dt:
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10/02/2001
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Application #:
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09440721
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Filing Dt:
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11/15/1999
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Title:
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CIRCUIT CONFIGURATION WITH A TEMPERATURE-DEPENDENT SEMICONDUCTOR COMPONENT TEST AND REPAIR LOGIC CIRCUIT
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Patent #:
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Issue Dt:
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07/30/2002
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Application #:
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09440803
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Filing Dt:
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11/15/1999
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Title:
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SEMICONDUCTOR MODULE FOR BURN-IN TEST CONFIGURATION
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