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Patent #:
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Issue Dt:
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11/06/2001
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Application #:
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09478312
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Filing Dt:
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01/06/2000
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Title:
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STACK CAPACITOR WITH IMPROVED PLUG CUNDUCTIVITY
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Patent #:
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Issue Dt:
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01/08/2002
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Application #:
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09481639
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Filing Dt:
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01/12/2000
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Title:
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CONVEYING SYSTEM
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Patent #:
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Issue Dt:
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01/08/2002
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Application #:
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09492654
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Filing Dt:
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01/27/2000
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Title:
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Method for improving the quality of metal conductor tracks on semiconductor structures
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Patent #:
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Issue Dt:
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07/03/2001
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Application #:
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09494774
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Filing Dt:
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01/31/2000
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Title:
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Method for fabricating an isolation trench using an auxiliary layer
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Patent #:
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Issue Dt:
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06/05/2001
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Application #:
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09498530
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Filing Dt:
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02/04/2000
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Title:
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Method for fabricating an integrated circuit configuration
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Patent #:
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Issue Dt:
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10/30/2001
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Application #:
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09504275
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Filing Dt:
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02/15/2000
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Title:
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Electrical test structure on a semiconductor substrate and test method
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Patent #:
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Issue Dt:
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02/13/2001
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Application #:
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09505379
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Filing Dt:
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02/16/2000
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Title:
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SEMICONDUCTOR MEMORY HAVING MEMORY BANK DECODERS DISPOSED SYMMETRICALLY ON A CHIP
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Patent #:
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Issue Dt:
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03/20/2001
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Application #:
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09510641
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Filing Dt:
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02/22/2000
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Title:
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Decoder connection configuration for memory chips with long bit lines
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Patent #:
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Issue Dt:
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08/27/2002
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Application #:
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09511812
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Filing Dt:
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02/24/2000
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Title:
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SEMICONDUCTOR MEMORY CONFIGURATION WITH DUMMY COMPONENTS ON CONTINUOUS DIFFUSION REGIONS
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Patent #:
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Issue Dt:
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12/05/2000
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Application #:
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09513587
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Filing Dt:
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02/25/2000
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Title:
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Integrated memory
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Patent #:
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Issue Dt:
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03/18/2003
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Application #:
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09514265
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Filing Dt:
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02/28/2000
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Title:
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METHOD FOR MOUNTING A SEMICONDUCTOR CHIP ON A CARRIER LAYER AND DEVICE FOR CARRYING OUT THE METHOD
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Patent #:
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Issue Dt:
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10/30/2001
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Application #:
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09514268
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Filing Dt:
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02/28/2000
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Title:
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Semiconductor memory configuration with a bit-line twist
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Patent #:
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Issue Dt:
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10/23/2001
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Application #:
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09519541
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Filing Dt:
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03/06/2000
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Title:
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Integrated circuit for producing two output clock signals at levels which do not overlap in time
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Patent #:
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Issue Dt:
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05/22/2001
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Application #:
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09523146
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Filing Dt:
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02/22/2000
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Title:
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Integrated semiconductor memory configuration with self-buffering of supply voltages
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Patent #:
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Issue Dt:
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07/09/2002
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Application #:
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09525820
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Filing Dt:
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03/15/2000
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Title:
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CONFIGURATION HAVING A FIELD-EFFECT TRANSISTOR HAVING A SHORT CHANNEL LENGTH AND AN ADJUSTABLE THRESHOLD VOLTAGE
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Patent #:
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Issue Dt:
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04/02/2002
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Application #:
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09546421
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Filing Dt:
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04/10/2000
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Title:
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Method for singling semiconductor components and semiconductor component singling device
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Patent #:
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Issue Dt:
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06/17/2003
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Application #:
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09550212
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Filing Dt:
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04/17/2000
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Title:
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CIRCUIT CONFIGURATION FOR THR BURN-IN TEST OF A SEMICONDUCTOR MODULE
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Patent #:
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Issue Dt:
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03/18/2003
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Application #:
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09553126
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Filing Dt:
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04/19/2000
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Title:
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CONFIGURATION FOR CARRYING OUT BURN-IN PROCESSING OPERATIONS OF SEMICONDUCTOR DEVICES AT WAFER LEVEL
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Patent #:
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Issue Dt:
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09/25/2001
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Application #:
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09553127
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Filing Dt:
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04/19/2000
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Title:
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Semiconductor memory configuration with a built-in-self-test
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Patent #:
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Issue Dt:
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09/25/2001
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Application #:
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09553128
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Filing Dt:
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04/19/2000
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Title:
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Semiconductor memory of the random access type with a bus system organized in two planes
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Patent #:
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Issue Dt:
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02/04/2003
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Application #:
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09560542
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Filing Dt:
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04/28/2000
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Title:
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BOTTOM RESIST
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Patent #:
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Issue Dt:
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07/10/2001
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Application #:
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09560545
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Filing Dt:
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04/28/2000
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Title:
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Integrated memory having sense amplifiers disposed on opposite sides of a cell array
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Patent #:
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Issue Dt:
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02/05/2002
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Application #:
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09566067
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Filing Dt:
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05/05/2000
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Title:
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Circuit configuration for programming an electrically programmable element
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Patent #:
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Issue Dt:
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11/06/2001
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Application #:
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09566936
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Filing Dt:
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05/08/2000
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Title:
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Method for cob mounting of electronic chip on a circuit board
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Patent #:
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Issue Dt:
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09/11/2001
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Application #:
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09568941
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Filing Dt:
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05/11/2000
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Title:
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Circuit configuration for monitoring states of a memory device
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Patent #:
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Issue Dt:
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04/02/2002
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Application #:
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09571486
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Filing Dt:
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05/15/2000
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Title:
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Circuit configuration for programming an electrically programmable element
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Patent #:
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Issue Dt:
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03/25/2003
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Application #:
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09574702
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Filing Dt:
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05/18/2000
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Title:
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METHOD OF TESTING A SEMICONDUCTOR MEMORY, AND SEMICONDUCTOR MEMORY WITH A TEST DEVICE
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Patent #:
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Issue Dt:
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11/19/2002
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Application #:
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09575056
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Filing Dt:
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05/19/2000
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Title:
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INTEGRATED MEMORY HAVING A REDUNDANCY FUNCTION
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Patent #:
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Issue Dt:
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01/14/2003
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Application #:
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09577060
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Filing Dt:
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05/22/2000
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Title:
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SEMICONDUCTOR MODULE WITH A NUMBER OF SEMICONDUCTOR CHIPS AND A CONDUCTIVE CONNECTION BETWEEN THE SEMICONDUCTOR CHIPS BY FLEXIBLE TAPES
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Patent #:
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Issue Dt:
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11/11/2003
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Application #:
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09577065
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Filing Dt:
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05/22/2000
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Title:
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SEMICONDUCTOR MODULE HAVING INTERCONNECTED SEMICONDUCTOR CHIPS DISPOSED ONE ABOVE THE OTHER
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Patent #:
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Issue Dt:
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07/29/2003
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Application #:
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09580034
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Filing Dt:
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05/26/2000
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Title:
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CIRCUIT CONFIGURATION FOR REPAIRING A SEMICONDUCTOR MEMORY
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Patent #:
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Issue Dt:
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09/04/2001
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Application #:
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09580982
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Filing Dt:
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05/30/2000
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Title:
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Integrated memory having redundant units of memory cells, and test method for the redundant units
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Patent #:
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Issue Dt:
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11/26/2002
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Application #:
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09580984
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Filing Dt:
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05/30/2000
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Title:
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CHIP CARRIER HAVING VENTILATION CHANNELS
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Patent #:
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Issue Dt:
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02/26/2002
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Application #:
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09580986
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Filing Dt:
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05/30/2000
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Title:
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Integrated memory with a block writing function and global amplifiers requiring less space
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Patent #:
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Issue Dt:
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10/23/2001
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Application #:
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09584329
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Filing Dt:
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05/30/2000
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Title:
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Integrated memory having 2-transistor/2-capacitor memory cells
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Patent #:
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Issue Dt:
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04/16/2002
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Application #:
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09603631
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Filing Dt:
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06/26/2000
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Title:
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INTEGRATED CIRCUIT WITH IMPROVED OFF CHIP DRIVERS
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Patent #:
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Issue Dt:
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08/20/2002
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Application #:
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09603749
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Filing Dt:
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06/26/2000
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Title:
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INTEGRATED MEMORY
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Patent #:
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Issue Dt:
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05/14/2002
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Application #:
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09607355
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Filing Dt:
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06/30/2000
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Title:
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Method for fabricating trenches having hallows along the trenches sidewall for storage capacitors of DRAM semiconductor memories
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Patent #:
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Issue Dt:
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08/27/2002
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Application #:
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09621430
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Filing Dt:
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07/21/2000
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Title:
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INTEGRATED SEMICONDUCTOR CIRCUIT WITH AN INCREASED OPERATING VOLTAGE
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Patent #:
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Issue Dt:
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02/24/2004
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Application #:
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09758300
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Filing Dt:
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01/10/2001
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Publication #:
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Pub Dt:
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08/23/2001
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Title:
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FERROELECTRIC READ/WRITE MEMORY WITH SERIES-CONNECTED MEMORY CELLS (CFRAM)
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Patent #:
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Issue Dt:
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09/17/2002
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Application #:
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09767805
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Filing Dt:
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01/22/2001
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Publication #:
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Pub Dt:
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10/25/2001
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Title:
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MEMORY CONFIGURATION INCLUDING A PLURALITY OF RESISTIVE FERROELECTRIC MEMORY CELLS
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Patent #:
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Issue Dt:
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06/11/2002
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Application #:
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09767807
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Filing Dt:
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01/22/2001
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Publication #:
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Pub Dt:
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02/14/2002
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Title:
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MEMORY CONFIGURATION INCLUDING A PLURALITY OF RESISTIVE FERROELECTRIC MEMORY CELLS
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Patent #:
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Issue Dt:
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09/28/2004
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Application #:
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09771912
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Filing Dt:
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01/29/2001
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Publication #:
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Pub Dt:
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09/06/2001
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Title:
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LEAD FRAME, CIRCUIT BOARD WITH LEAD FRAME, AND METHOD FOR PRODUCING THE LEAD FRAME
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Patent #:
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Issue Dt:
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08/20/2002
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Application #:
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09774743
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Filing Dt:
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01/31/2001
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Publication #:
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Pub Dt:
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01/10/2002
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Title:
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MEMORY CELL WITH A STACKED CAPACITOR
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Patent #:
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Issue Dt:
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08/13/2002
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Application #:
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09793344
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Filing Dt:
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02/26/2001
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Publication #:
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Pub Dt:
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02/14/2002
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Title:
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MEMORY SYSTEM
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Patent #:
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Issue Dt:
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03/23/2004
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Application #:
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09801209
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Filing Dt:
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03/07/2001
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Publication #:
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Pub Dt:
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11/08/2001
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Title:
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FERROELECTRIC TRANSISTOR, USE THEREOF IN A MEMORY CELL CONFUGURATION AND METHOD OF PRODUCING THE FERROELECTRIC TRANSISTOR
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Patent #:
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Issue Dt:
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12/17/2002
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Application #:
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09801210
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Filing Dt:
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03/07/2001
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Publication #:
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Pub Dt:
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09/27/2001
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Title:
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MAGNETORESISTIVE ELEMENT AND USE THEREOF AS A MEMORY ELEMENT IN A MEMORY CELL CONFIGURATION
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Patent #:
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Issue Dt:
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08/17/2004
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Application #:
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09811881
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Filing Dt:
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03/19/2001
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Publication #:
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Pub Dt:
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09/27/2001
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Title:
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SELECTIVELY DEACTIVATING A FIRST CONTROL LOOP IN A DUAL CONTROL LOOP CIRCUIT DURING DATA TRANSMISSION
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Patent #:
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Issue Dt:
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05/21/2002
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Application #:
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09817578
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Filing Dt:
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03/26/2001
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Publication #:
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Pub Dt:
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11/08/2001
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Title:
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Circuit configuration for generating a reference voltage for reading a ferroelectric memory
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Patent #:
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Issue Dt:
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02/26/2002
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Application #:
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09820235
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Filing Dt:
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03/28/2001
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Publication #:
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Pub Dt:
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11/08/2001
| | | | |
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Title:
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Integrated memory having a differential sense amplifier
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Patent #:
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Issue Dt:
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08/19/2003
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Application #:
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09821853
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Filing Dt:
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03/30/2001
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Title:
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SUBSTRATE ASSEMBLY HAVING A DEPRESSION SUITABLE FOR AN INTEGRATED CIRCUIT CONFIGURATION AND METHOD FOR ITS FABRICATION
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Patent #:
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Issue Dt:
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04/02/2002
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Application #:
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09821964
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Filing Dt:
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03/30/2001
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Publication #:
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Pub Dt:
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11/22/2001
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Title:
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Magnetoresistive memory having elevated interference immunity
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Patent #:
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Issue Dt:
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06/17/2003
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Application #:
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09822019
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Filing Dt:
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03/30/2001
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Publication #:
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Pub Dt:
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10/18/2001
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Title:
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MAGNETORESISTIVE MEMORY WITH A LOW CURRENT DENSITY
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Patent #:
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Issue Dt:
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05/21/2002
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Application #:
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09822027
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Filing Dt:
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03/29/2001
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Publication #:
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Pub Dt:
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10/04/2001
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Title:
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DECODER ELEMENT FOR PRODUCING AN OUTPUT SIGNAL HAVING THREE DIFFERENT POTENTIALS
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Patent #:
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Issue Dt:
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11/12/2002
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Application #:
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09822028
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Filing Dt:
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03/29/2001
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Publication #:
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Pub Dt:
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01/24/2002
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Title:
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DECODER ELEMENT FOR GENERATING AN OUTPUT SIGNAL HAVING THREE DIFFERENT POTENTIALS AND AN OPERATING METHOD FOR THE DECODER ELEMENT
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Patent #:
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Issue Dt:
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03/25/2003
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Application #:
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09849910
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Filing Dt:
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05/04/2001
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Publication #:
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Pub Dt:
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11/22/2001
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Title:
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FERROELECTRIC TRANSISTOR AND METHOD FOR FABRICATING IT
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Patent #:
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Issue Dt:
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07/01/2003
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Application #:
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09850585
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Filing Dt:
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05/07/2001
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Publication #:
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Pub Dt:
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12/27/2001
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Title:
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A METHOD FOR PREVENTING ETCHING-INDUCED DAMAGE TO A METAL OXIDE FILM BY PATTERNING THE FILM AFTER A NUCLEATION ANNEAL BUT WHILE STILL AMORPHOUS AND THEN THERMALLY ANNEALING TO CRYSTALLIZE
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Patent #:
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Issue Dt:
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08/20/2002
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Application #:
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09854259
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Filing Dt:
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05/10/2001
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Publication #:
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Pub Dt:
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11/01/2001
| | | | |
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Title:
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MEMORY CELL CONFIGURATION
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Patent #:
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Issue Dt:
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02/04/2003
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Application #:
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09861431
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Filing Dt:
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05/18/2001
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Publication #:
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Pub Dt:
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02/07/2002
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Title:
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FIELD-EFFECT-CONTROLLED TRANSISTOR AND METHOD FOR FABRICATING THE TRANSISTOR
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Patent #:
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Issue Dt:
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01/28/2003
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Application #:
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09863925
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Filing Dt:
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05/23/2001
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Title:
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CAPACITOR WITH HIGH-EPSILON DIELECTRIC OR FERROELECTRIC MATERIAL BASED ON THE FIN STACK PRINCIPLE
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Patent #:
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Issue Dt:
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05/28/2002
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Application #:
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09888022
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Filing Dt:
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06/22/2001
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Publication #:
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Pub Dt:
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01/10/2002
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Title:
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INTEGRATED MEMORY WITH REDUNDANCY AND METHOD FOR REPAIRING AN INTEGRATED MEMORY
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Patent #:
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Issue Dt:
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04/04/2006
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Application #:
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10009979
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Filing Dt:
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03/27/2002
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Title:
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COMPUTER-ASSISTED METHOD FOR THE PARALLEL CALCULATION OF THE OPERATING POINT OF ELECTRIC CIRCUITS
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Patent #:
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Issue Dt:
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03/18/2003
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Application #:
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10187759
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Filing Dt:
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07/02/2002
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Publication #:
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Pub Dt:
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11/21/2002
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Title:
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INTEGRATED SEMICONDUCTOR CIRCUIT WITH AN INCREASED OPERATING VOLTAGE
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