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NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:024120/0001   Pages: 253
Recorded: 02/18/2010
Attorney Dkt #:609612800100
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 161
Page 1 of 2
Pages: 1 2
1
Patent #:
Issue Dt:
09/08/1998
Application #:
08824703
Filing Dt:
04/14/1997
Title:
METHOD OF FILLING SHALLOW TRENCHES
2
Patent #:
Issue Dt:
08/15/2000
Application #:
08850093
Filing Dt:
05/01/1997
Title:
SELF-ALIGNED POLYSILICON FET DEVICES ISOLATED WITH MASKLESS SHALLOW TRENCH ISOLATION AND GATE CONDUCTOR FILL TECHNOLOGY AND METHOD OF MANUFACTURE THEREOF
3
Patent #:
Issue Dt:
12/14/1999
Application #:
08868555
Filing Dt:
06/04/1997
Title:
METHOD FOR FORMING A CAPACITAR
4
Patent #:
Issue Dt:
08/08/2000
Application #:
08873100
Filing Dt:
06/11/1997
Title:
METHOD OF FABRICATING A RANDOM ACCESS MEMEORY CELL
5
Patent #:
Issue Dt:
11/03/1998
Application #:
08879726
Filing Dt:
06/20/1997
Title:
IMPROVED REDUNDANT CIRCUITS AND METHODS THEREFOR
6
Patent #:
Issue Dt:
05/04/1999
Application #:
08882056
Filing Dt:
06/25/1997
Title:
METHOD FOR MAKING SILICA STRAIN TEST STRUCTURES
7
Patent #:
Issue Dt:
06/13/2000
Application #:
08882057
Filing Dt:
06/25/1997
Title:
METHOD OF REDUCING THE FORMATION OF WATERMARKS ON SEMICONDUCTOR WAFERS
8
Patent #:
Issue Dt:
07/21/1998
Application #:
08883356
Filing Dt:
06/26/1997
Title:
INTEGRATED CIRCUIT DEVICES INCLUDING SHALLOW TRENCH ISOLATION
9
Patent #:
Issue Dt:
03/09/1999
Application #:
08884081
Filing Dt:
06/27/1997
Title:
APPARATUS FOR CONTROLLING CIRCUIT RESPONSE DURING POWER-UP
10
Patent #:
Issue Dt:
03/23/1999
Application #:
08884118
Filing Dt:
06/27/1997
Title:
IMPROVED CHEMICAL MECHANICAL POLISHING PAD CONDITIONER
11
Patent #:
Issue Dt:
03/07/2000
Application #:
08884729
Filing Dt:
06/30/1997
Title:
IMPROVED DUAL DAMASCENE STRUCTURE
12
Patent #:
Issue Dt:
04/18/2000
Application #:
08884732
Filing Dt:
06/30/1997
Title:
FORMATION OF SUB-GROUNDRULE FEATURES
13
Patent #:
Issue Dt:
10/13/1998
Application #:
08884853
Filing Dt:
06/30/1997
Title:
DYNAMIC RANDOM ACCESS MEMORY ARRAYS AND METHODS THEREFOR
14
Patent #:
Issue Dt:
11/03/1998
Application #:
08884854
Filing Dt:
06/30/1997
Title:
TECHNIQUES FOR REDUCING REDUNDANT ELEMENT FUSES IN A DYNAMIC RANDOM ACCESS MEMORY ARRAY
15
Patent #:
Issue Dt:
02/23/1999
Application #:
08884855
Filing Dt:
06/30/1997
Title:
DYNAMIC ACCESS MEMORY EQUALIZER CIRCUITS AND METHODS THEREFOR
16
Patent #:
Issue Dt:
08/10/1999
Application #:
08884860
Filing Dt:
06/30/1997
Title:
CMOS INTEGRATED CIRCUITS WITH REDUCED SUBSTRATE DEFECTS
17
Patent #:
Issue Dt:
10/09/2001
Application #:
08884861
Filing Dt:
06/30/1997
Title:
METHOD OF FORMING MULTI-LEVEL COPLANAR METAL/INSULATOR FILMS USING DUAL DAMASCENE WITH SACRIFICIAL FLOWABLE OXIDE
18
Patent #:
Issue Dt:
05/04/1999
Application #:
08884862
Filing Dt:
06/30/1997
Title:
METHOD OF REDUCING LOADING VARIATION DURING ETCH PROCESSING
19
Patent #:
Issue Dt:
03/30/1999
Application #:
08885329
Filing Dt:
06/30/1997
Title:
OCD WITH LOW OUTPUT CAPACITANCE
20
Patent #:
Issue Dt:
11/02/1999
Application #:
08895061
Filing Dt:
07/16/1997
Title:
VARIABLE DOMAIN REDUNDANCY REPLACEMENT CONFIGURATION FOR A MEMORY DEVICE
21
Patent #:
Issue Dt:
10/05/1999
Application #:
08900270
Filing Dt:
07/25/1997
Title:
PROCESS FOR FABRICATING LAYERED SUPERLATTICE MATERIALS AND AB03 TYPE METAL OXIDES WITHOUT EXPOSURE TO OXYGEN AT HIGH TEMPERATURES
22
Patent #:
Issue Dt:
10/12/1999
Application #:
08901986
Filing Dt:
07/29/1997
Title:
METHOD OF MANUFACTURING A SEMICONDUCTOR STRUCTURE HAVING A CRYSTALLINE LAYER
23
Patent #:
Issue Dt:
11/21/2000
Application #:
08916636
Filing Dt:
08/22/1997
Title:
METHOD OF MANUFACTURING A SHALLOW TRENCH ISOLATION STRUCTURE FOR A SEMICONDUCTOR DEVICE
24
Patent #:
Issue Dt:
11/10/1998
Application #:
08923459
Filing Dt:
09/04/1997
Title:
DIMENSION PROGRAMMABLE FUSEBANKS AND METHODS FOR MAKING THE SAME
25
Patent #:
Issue Dt:
08/17/1999
Application #:
08929711
Filing Dt:
09/15/1997
Title:
SEMICONDUCTOR WAFER TEMPERATURE MEASUREMENT AND CONTROL THEREOF USING GAS TEMPERATURE MEASUREMENT
26
Patent #:
Issue Dt:
03/07/2000
Application #:
08932925
Filing Dt:
09/19/1997
Title:
APPARATUS AND METHOD FOR HIGH-SPEED WORDLINE DRIVING WITH LOW AREA OVERHEAD
27
Patent #:
Issue Dt:
05/04/1999
Application #:
08933955
Filing Dt:
09/19/1997
Title:
TECHNIQUES FOR FORMING ELECTRICALLY BLOWABLE FUSES ON AN INTEGRATED CIRCUIT
28
Patent #:
Issue Dt:
03/25/2003
Application #:
08934101
Filing Dt:
09/19/1997
Title:
SPATIALLY UNIFORM GAS SUPPLY AND PUMP CONFIGURATION FOR LARGE WAFER DIAMETERS
29
Patent #:
Issue Dt:
04/06/1999
Application #:
08937526
Filing Dt:
09/25/1997
Title:
FORMATION OF A BOTTLE SHAPED TRENCH
30
Patent #:
Issue Dt:
12/08/1998
Application #:
08937528
Filing Dt:
09/25/1997
Title:
FLOATING BITLINE TEST MODE WITH DIGITALLY CONTROLLABLE BITLINE EQUALIZERS
31
Patent #:
Issue Dt:
06/20/2000
Application #:
08937570
Filing Dt:
09/25/1997
Title:
SEMICONDUCTOR MEMORY HAVING REDUNDANCY CIRCUIT
32
Patent #:
Issue Dt:
09/28/1999
Application #:
08937571
Filing Dt:
09/25/1997
Title:
A METHOD AND APPARATUS FOR REDUCING THE BIAS CURRENT IN A REFERENCE VOLTAGE CIRCUIT
33
Patent #:
Issue Dt:
09/21/1999
Application #:
08937572
Filing Dt:
09/25/1997
Title:
METHOD OF END POINT DETECTION USING A SINUSOIDAL INTERFERENCE SIGNAL FOR A WET ETCH PROCESS
34
Patent #:
Issue Dt:
10/24/2000
Application #:
08937781
Filing Dt:
09/25/1997
Title:
METHOD OF FABRICATING SEMICONDUCTOR CHIPS WITH SILICIDE AND IMPLANTED JUNCTIONS
35
Patent #:
Issue Dt:
04/04/2000
Application #:
08938072
Filing Dt:
09/26/1997
Title:
METALIZATION SYSTEM HAVING AN ENHANCED THERMAL CONDUCTIVITY
36
Patent #:
Issue Dt:
03/02/1999
Application #:
08938073
Filing Dt:
09/26/1997
Title:
SPACE-EFFICIENT MDQ SWITCH PLACEMENT
37
Patent #:
Issue Dt:
11/03/1998
Application #:
08938074
Filing Dt:
09/26/1997
Title:
SEMICONDUCTOR MEMORY HAVING SPACE-EFFICIENT LAYOUT
38
Patent #:
Issue Dt:
01/11/2000
Application #:
08938196
Filing Dt:
09/26/1997
Title:
BUFFER LAYER FOR IMPROVING CONTROL OF LAYER THICKNESS
39
Patent #:
Issue Dt:
08/10/1999
Application #:
08939148
Filing Dt:
09/29/1997
Title:
DEPOSITION OF CARBON INTO NITRIDE LAYER FOR IMPROVED SELECTIVITY OF OXIDE TO NITRIDE ETCHRATE FOR SELF ALIGNED CONTACT ETCHING
40
Patent #:
Issue Dt:
11/02/1999
Application #:
08939208
Filing Dt:
09/29/1997
Title:
MULTI-LEVEL CONDUCTIVE STRUCTURE INCLUDING LOW CAPACITANCE MATERIAL
41
Patent #:
Issue Dt:
02/02/1999
Application #:
08939216
Filing Dt:
09/29/1997
Title:
TECHNIQUES FOR ETCHING A SILICON DIOXIDE-CONTAINING LAYER
42
Patent #:
Issue Dt:
09/15/1998
Application #:
08939547
Filing Dt:
09/29/1997
Title:
APPARATUS AND METHOD FOR IMPROVED WASHING AND DRYING OF SEMICONDUCTOR WAFERS
43
Patent #:
Issue Dt:
05/25/1999
Application #:
08940233
Filing Dt:
09/30/1997
Title:
REDUCTION OF PAD EROSION
44
Patent #:
Issue Dt:
04/23/2002
Application #:
08940235
Filing Dt:
09/30/1997
Title:
RELIABLE POLICIDE GATE STACK WITH REDUCED SHEET RESISTANCE AND THICKNESS
45
Patent #:
Issue Dt:
01/16/2001
Application #:
08940236
Filing Dt:
09/30/1997
Title:
SPACERS TO BLOCK DEEP JUNCTION IMPLANTS AND SILICIDE FORMATION IN INTEGRATED CIRCUITS
46
Patent #:
Issue Dt:
11/09/1999
Application #:
08940237
Filing Dt:
09/30/1997
Title:
REDUCED PARASITIC LEAKAGE IN SEMICONDUCTOR DEVICES
47
Patent #:
Issue Dt:
03/09/1999
Application #:
08940650
Filing Dt:
09/30/1997
Title:
PLANARIZATION OF A NON-CONFORMAL DEVICE LAYER IN SEMICONDUCTOR FABRICATION
48
Patent #:
Issue Dt:
05/15/2001
Application #:
08940806
Filing Dt:
09/30/1997
Title:
METHODS FOR PERFORMING PLANARIZATION AND RECESS ETCHES AND APPARATUS THEREFOR
49
Patent #:
Issue Dt:
10/03/2000
Application #:
08940807
Filing Dt:
09/30/1997
Title:
SOFT PASSIVATION LAYER IN SEMICONDUCTOR FABRICATION
50
Patent #:
Issue Dt:
07/13/1999
Application #:
08940861
Filing Dt:
09/29/1997
Title:
SPACE-EFFICIENT SEMICONDUCTOR MEMORY HAVING HIERARCHICAL COLUMN SELECT LINE ARCHITECTURE
51
Patent #:
Issue Dt:
08/17/1999
Application #:
08940862
Filing Dt:
09/29/1997
Title:
CONSTANT CURRENT CMOS OUTPUT DRIVER CIRCUIT WITH DUAL GATE TRANSISTOR DEVICES
52
Patent #:
Issue Dt:
02/01/2000
Application #:
08940891
Filing Dt:
09/30/1997
Title:
HARD ETCH MASK
53
Patent #:
Issue Dt:
06/06/2000
Application #:
08940892
Filing Dt:
09/30/1997
Title:
METHOD FOR PATTERNING INTEGRATED CIRCUIT CONDUCTORS
54
Patent #:
Issue Dt:
05/23/2000
Application #:
08940895
Filing Dt:
09/30/1997
Title:
DUAL DAMASCENE PROCESS FOR METAL LAYERS AND ORGANIC INTERMETAL LAYERS
55
Patent #:
Issue Dt:
08/24/1999
Application #:
08940899
Filing Dt:
09/30/1997
Title:
POWER-ON DETECTION AND ENABLING CIRCUIT WITH VERY FAST DETECTION OF POWER-OFF
56
Patent #:
Issue Dt:
09/21/1999
Application #:
08941093
Filing Dt:
09/30/1997
Title:
ENDPOINT DETECTION METHOD AND APPARATUS
57
Patent #:
Issue Dt:
07/18/2000
Application #:
08941600
Filing Dt:
09/30/1997
Title:
REDUCTION OF GATE-INDUCED DRAIN LEAKAGE IN SEMICONDUCTOR DEVICES
58
Patent #:
Issue Dt:
08/01/2000
Application #:
08942273
Filing Dt:
09/30/1997
Title:
GAPFILL OF SEMICONDUCTOR STRUCTURE USING DOPED SILICATE GLASSES
59
Patent #:
Issue Dt:
10/12/1999
Application #:
08942275
Filing Dt:
09/30/1997
Title:
SEMICONDUCTOR MEMORY HAVING HIERARCHICAL BIT LINE ARCHITECTURE WITH NON-UNIFORM LOCAL BIT LINES
60
Patent #:
Issue Dt:
01/26/1999
Application #:
08943080
Filing Dt:
10/01/1997
Title:
FERROMAGNETIC MEMORY USING SOFT MAGNETIC MATERIAL AND HARD MAGNETIC MATERIAL
61
Patent #:
Issue Dt:
02/02/1999
Application #:
08943910
Filing Dt:
09/30/1997
Title:
REDUCING OXIDATION STRESS IN THE FABRICATION OF DEVICES
62
Patent #:
Issue Dt:
12/19/2000
Application #:
08978354
Filing Dt:
11/25/1997
Title:
MASK BLANK AND METHOD OF PRODUCING MASK
63
Patent #:
Issue Dt:
01/18/2000
Application #:
08992378
Filing Dt:
12/17/1997
Title:
MEMORY WITH WORD LINE VOLTAGE CONTROL
64
Patent #:
Issue Dt:
12/08/1998
Application #:
08992379
Filing Dt:
12/17/1997
Title:
MEMORY ARRAY WITH REDUCED CHARGING CURRENT
65
Patent #:
Issue Dt:
06/29/1999
Application #:
08993537
Filing Dt:
12/18/1997
Title:
SEMICONDUCTOR MEMORY HAVING HIERARCHICAL BIT LINE ARCHITECTURE WITH INTERLEAVED MASTER BITLINES
66
Patent #:
Issue Dt:
05/30/2000
Application #:
08993538
Filing Dt:
12/18/1997
Title:
SEMICONDUCTOR MEMORY HAVING HIERARCHICAL BIT LINE AND/OR WORD LINE ARCHITECTURE
67
Patent #:
Issue Dt:
12/07/1999
Application #:
08993743
Filing Dt:
12/19/1997
Title:
METHOD OF FORMING DOPANT OUTDIFFUSION CONTROL STRUCTURE INCLUDING SELECTIVELY GROWN SILICON NITRIDE IN A TRENCH CAPACITOR OF A DRAM CELL
68
Patent #:
Issue Dt:
02/16/1999
Application #:
08996576
Filing Dt:
12/23/1997
Title:
METHOD AND APPARATUS FOR DETERMINING WAFER WARPAGE FOR OPTIMIZED ELECTROSTATIC CHUCK CLAMPING VOLTAGE
69
Patent #:
Issue Dt:
05/11/1999
Application #:
08997460
Filing Dt:
12/23/1997
Title:
METHOD FOR DETECTING UNDERETCHED VIAS
70
Patent #:
Issue Dt:
03/07/2000
Application #:
08997682
Filing Dt:
12/23/1997
Title:
DUAL DAMASCENE WITH BOND PADS
71
Patent #:
Issue Dt:
09/26/2000
Application #:
08998856
Filing Dt:
12/29/1997
Title:
REDUCED PAD EROSION
72
Patent #:
Issue Dt:
02/02/1999
Application #:
08998857
Filing Dt:
12/29/1997
Title:
WAFER SURFACE CLEANING APPARATUS AND METHOD
73
Patent #:
Issue Dt:
03/07/2000
Application #:
08998858
Filing Dt:
12/29/1997
Title:
REDUCTION OF BLACK SILICON IN SEMICONDUCTOR FABRICATION
74
Patent #:
Issue Dt:
05/16/2000
Application #:
08999926
Filing Dt:
06/23/1997
Title:
CONTROL OF CRITICAL DIMENSIONS THROUGH MEASUREMENT OF ABOSRBED RADIATION
75
Patent #:
Issue Dt:
10/19/1999
Application #:
09000625
Filing Dt:
12/30/1997
Title:
REDUCED STAND BY POWER CONSUMPTION IN A DRAM
76
Patent #:
Issue Dt:
11/01/2005
Application #:
09000626
Filing Dt:
12/30/1997
Title:
RECESSED SHALLOW TRENCH ISOLATION STRUCTURE NITRIDE LINER AND METHOD FOR MAKING SAME
77
Patent #:
Issue Dt:
12/11/2001
Application #:
09030227
Filing Dt:
02/25/1998
Title:
CONTACT BETWEEN A MONOCRYSTALLINE SILICON REGION AND A POLYCRYSTALLINE SILICON STRUCTURE AND METHOD FOR PRODUCING SUCH A CONTACT
78
Patent #:
Issue Dt:
05/30/2000
Application #:
09030406
Filing Dt:
02/25/1998
Title:
METHOD FOR PRODUCING A POLYCRYSTALLINE SILICON STRUCTURE AND POLYCRYSTALLINE SILICON LAYER TO BE PRODUCED BY THE METHOD
79
Patent #:
Issue Dt:
06/20/2000
Application #:
09049699
Filing Dt:
03/27/1998
Title:
METHOD AND APPARATUS FOR SIZE OPTIMIZATION OF STORAGE UNITS
80
Patent #:
Issue Dt:
08/10/1999
Application #:
09095985
Filing Dt:
06/11/1998
Title:
APPARATUS AND METHOD FOR IMPROVED WASHING AND DRYING OF SEMICONDUCTOR WAFERS
81
Patent #:
Issue Dt:
10/07/2003
Application #:
09137179
Filing Dt:
08/20/1998
Title:
ETCHING COMPOSITION AND USE THEREOF
82
Patent #:
Issue Dt:
08/17/1999
Application #:
09183246
Filing Dt:
10/30/1998
Title:
RECESSED SHALLOW TRENCH ISOLATION STRUCTURE NITRIDE LINER AND METHOD FOR MAKING SAME
83
Patent #:
Issue Dt:
11/30/1999
Application #:
09187153
Filing Dt:
11/06/1998
Title:
APPARATUS FOR CONTROLLING CIRCUIT RESPONSE DURING POWER-UP
84
Patent #:
Issue Dt:
12/14/1999
Application #:
09187165
Filing Dt:
11/06/1998
Title:
PLANARIZATION OF A NON-CONFORMAL DEVICE LAYER IN SEMICONDUCTOR FABRICATION
85
Patent #:
Issue Dt:
10/05/1999
Application #:
09197360
Filing Dt:
11/20/1998
Title:
ANTISENSE MODULATION OF INHIBITOR-KAPPA B KINASE-ALPHA EXPRESSION
86
Patent #:
Issue Dt:
04/02/2002
Application #:
09197371
Filing Dt:
11/20/1998
Title:
PLASTIC COMPOSITIONS FOR SHEATHING A METAL OR SEMICONDUCTOR BODY
87
Patent #:
Issue Dt:
12/19/2000
Application #:
09215011
Filing Dt:
12/17/1998
Title:
REDUCED PARASITIC LEAKAGE IN SEMICONDUCTOR DEVICES
88
Patent #:
Issue Dt:
08/01/2000
Application #:
09228610
Filing Dt:
01/12/1999
Title:
AN ADJUSTABLE DELAY CIRCUIT
89
Patent #:
Issue Dt:
11/14/2000
Application #:
09228611
Filing Dt:
01/12/1999
Title:
DRAM CELL ARRANGEMENT AND METHOD FOR ITS PRODUCTION
90
Patent #:
Issue Dt:
01/21/2003
Application #:
09232081
Filing Dt:
01/15/1999
Title:
TRENCH CAPACITOR WITH INSULATION COLLAR AND METHOD FOR PRODUCING THE TRENCH CAPACITOR
91
Patent #:
Issue Dt:
11/30/1999
Application #:
09232083
Filing Dt:
01/15/1999
Title:
MEMORY CELL CONFIGURATION AND METHOD FOR ITS FABRICATION
92
Patent #:
Issue Dt:
04/10/2001
Application #:
09243296
Filing Dt:
02/02/1999
Title:
INTEGRATED MEMORY
93
Patent #:
Issue Dt:
07/10/2001
Application #:
09250362
Filing Dt:
02/12/1999
Title:
MEMORY CELL CONFIGURATION AND CORRESPONDING FABRICATION METHOD
94
Patent #:
Issue Dt:
03/19/2002
Application #:
09250516
Filing Dt:
02/16/1999
Title:
CIRCUIT ARRANGEMENT WITH AT LEAST ONE CAPACITOR
95
Patent #:
Issue Dt:
11/30/1999
Application #:
09251611
Filing Dt:
02/17/1999
Title:
SEMICONDUCTOR WAFER TEMPERATURE MEASUREMENT AND CONTROL THEREOF USING GAS TEMPERATURE MEASUREMENT
96
Patent #:
Issue Dt:
02/22/2000
Application #:
09258940
Filing Dt:
03/01/1999
Title:
INTEGRATED MEMORY
97
Patent #:
Issue Dt:
06/04/2002
Application #:
09261100
Filing Dt:
03/02/1999
Title:
INTEGRATED CIRCUIT AND METHOD FOR TESTING IT
98
Patent #:
Issue Dt:
08/01/2000
Application #:
09272077
Filing Dt:
03/18/1999
Title:
DRAM CELL ARRANGEMENT
99
Patent #:
Issue Dt:
08/28/2001
Application #:
09272968
Filing Dt:
03/19/1999
Title:
MOS TRANSISTOR IN A SINGLE-TRANSISTOR MEMORY CELL HAVING A LOCALLY THICKENED GATE OXIDE, AND PRODUCTION PROCESS
100
Patent #:
Issue Dt:
03/28/2000
Application #:
09273648
Filing Dt:
03/23/1999
Title:
METHOD FOR PROGRAMMING A ROM CELL ARRANGEMENT
Assignor
1
Exec Dt:
03/31/1999
Assignee
1
ST.-MARTIN-STR. 53
MUNICH, GERMANY 81541
Correspondence name and address
BARRY E. BRETSCHNEIDER
C/O MORRISON & FOERSTER LLP
1650 TYSONS BOULEVARD, SUITE 400
MCLEAN, VIRGINIA 22102

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