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Patent #:
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Issue Dt:
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09/08/1998
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Application #:
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08824703
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Filing Dt:
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04/14/1997
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Title:
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METHOD OF FILLING SHALLOW TRENCHES
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Patent #:
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Issue Dt:
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08/15/2000
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Application #:
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08850093
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Filing Dt:
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05/01/1997
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Title:
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SELF-ALIGNED POLYSILICON FET DEVICES ISOLATED WITH MASKLESS SHALLOW TRENCH ISOLATION AND GATE CONDUCTOR FILL TECHNOLOGY AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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12/14/1999
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Application #:
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08868555
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Filing Dt:
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06/04/1997
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Title:
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METHOD FOR FORMING A CAPACITAR
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Patent #:
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Issue Dt:
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08/08/2000
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Application #:
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08873100
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Filing Dt:
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06/11/1997
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Title:
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METHOD OF FABRICATING A RANDOM ACCESS MEMEORY CELL
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Patent #:
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Issue Dt:
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11/03/1998
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Application #:
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08879726
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Filing Dt:
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06/20/1997
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Title:
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IMPROVED REDUNDANT CIRCUITS AND METHODS THEREFOR
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Patent #:
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Issue Dt:
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05/04/1999
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Application #:
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08882056
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Filing Dt:
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06/25/1997
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Title:
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METHOD FOR MAKING SILICA STRAIN TEST STRUCTURES
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Patent #:
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Issue Dt:
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06/13/2000
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Application #:
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08882057
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Filing Dt:
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06/25/1997
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Title:
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METHOD OF REDUCING THE FORMATION OF WATERMARKS ON SEMICONDUCTOR WAFERS
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Patent #:
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Issue Dt:
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07/21/1998
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Application #:
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08883356
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Filing Dt:
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06/26/1997
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Title:
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INTEGRATED CIRCUIT DEVICES INCLUDING SHALLOW TRENCH ISOLATION
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Patent #:
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Issue Dt:
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03/09/1999
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Application #:
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08884081
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Filing Dt:
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06/27/1997
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Title:
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APPARATUS FOR CONTROLLING CIRCUIT RESPONSE DURING POWER-UP
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Patent #:
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Issue Dt:
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03/23/1999
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Application #:
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08884118
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Filing Dt:
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06/27/1997
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Title:
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IMPROVED CHEMICAL MECHANICAL POLISHING PAD CONDITIONER
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Patent #:
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Issue Dt:
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03/07/2000
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Application #:
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08884729
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Filing Dt:
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06/30/1997
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Title:
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IMPROVED DUAL DAMASCENE STRUCTURE
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Patent #:
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Issue Dt:
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04/18/2000
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Application #:
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08884732
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Filing Dt:
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06/30/1997
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Title:
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FORMATION OF SUB-GROUNDRULE FEATURES
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Patent #:
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Issue Dt:
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10/13/1998
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Application #:
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08884853
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Filing Dt:
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06/30/1997
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Title:
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DYNAMIC RANDOM ACCESS MEMORY ARRAYS AND METHODS THEREFOR
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Patent #:
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Issue Dt:
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11/03/1998
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Application #:
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08884854
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Filing Dt:
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06/30/1997
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Title:
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TECHNIQUES FOR REDUCING REDUNDANT ELEMENT FUSES IN A DYNAMIC RANDOM ACCESS MEMORY ARRAY
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Patent #:
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Issue Dt:
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02/23/1999
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Application #:
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08884855
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Filing Dt:
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06/30/1997
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Title:
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DYNAMIC ACCESS MEMORY EQUALIZER CIRCUITS AND METHODS THEREFOR
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Patent #:
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Issue Dt:
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08/10/1999
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Application #:
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08884860
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Filing Dt:
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06/30/1997
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Title:
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CMOS INTEGRATED CIRCUITS WITH REDUCED SUBSTRATE DEFECTS
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Patent #:
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Issue Dt:
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10/09/2001
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Application #:
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08884861
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Filing Dt:
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06/30/1997
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Title:
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METHOD OF FORMING MULTI-LEVEL COPLANAR METAL/INSULATOR FILMS USING DUAL DAMASCENE WITH SACRIFICIAL FLOWABLE OXIDE
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Patent #:
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Issue Dt:
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05/04/1999
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Application #:
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08884862
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Filing Dt:
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06/30/1997
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Title:
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METHOD OF REDUCING LOADING VARIATION DURING ETCH PROCESSING
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Patent #:
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Issue Dt:
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03/30/1999
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Application #:
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08885329
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Filing Dt:
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06/30/1997
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Title:
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OCD WITH LOW OUTPUT CAPACITANCE
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Patent #:
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Issue Dt:
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11/02/1999
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Application #:
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08895061
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Filing Dt:
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07/16/1997
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Title:
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VARIABLE DOMAIN REDUNDANCY REPLACEMENT CONFIGURATION FOR A MEMORY DEVICE
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Patent #:
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Issue Dt:
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10/05/1999
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Application #:
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08900270
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Filing Dt:
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07/25/1997
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Title:
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PROCESS FOR FABRICATING LAYERED SUPERLATTICE MATERIALS AND AB03 TYPE METAL OXIDES WITHOUT EXPOSURE TO OXYGEN AT HIGH TEMPERATURES
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Patent #:
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Issue Dt:
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10/12/1999
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Application #:
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08901986
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Filing Dt:
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07/29/1997
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Title:
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METHOD OF MANUFACTURING A SEMICONDUCTOR STRUCTURE HAVING A CRYSTALLINE LAYER
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Patent #:
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|
Issue Dt:
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11/21/2000
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Application #:
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08916636
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Filing Dt:
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08/22/1997
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Title:
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METHOD OF MANUFACTURING A SHALLOW TRENCH ISOLATION STRUCTURE FOR A SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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11/10/1998
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Application #:
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08923459
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Filing Dt:
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09/04/1997
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Title:
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DIMENSION PROGRAMMABLE FUSEBANKS AND METHODS FOR MAKING THE SAME
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Patent #:
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Issue Dt:
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08/17/1999
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Application #:
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08929711
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Filing Dt:
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09/15/1997
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Title:
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SEMICONDUCTOR WAFER TEMPERATURE MEASUREMENT AND CONTROL THEREOF USING GAS TEMPERATURE MEASUREMENT
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Patent #:
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Issue Dt:
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03/07/2000
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Application #:
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08932925
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Filing Dt:
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09/19/1997
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Title:
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APPARATUS AND METHOD FOR HIGH-SPEED WORDLINE DRIVING WITH LOW AREA OVERHEAD
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Patent #:
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Issue Dt:
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05/04/1999
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Application #:
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08933955
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Filing Dt:
|
09/19/1997
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Title:
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TECHNIQUES FOR FORMING ELECTRICALLY BLOWABLE FUSES ON AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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03/25/2003
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Application #:
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08934101
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Filing Dt:
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09/19/1997
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Title:
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SPATIALLY UNIFORM GAS SUPPLY AND PUMP CONFIGURATION FOR LARGE WAFER DIAMETERS
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Patent #:
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Issue Dt:
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04/06/1999
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Application #:
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08937526
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Filing Dt:
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09/25/1997
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Title:
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FORMATION OF A BOTTLE SHAPED TRENCH
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Patent #:
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|
Issue Dt:
|
12/08/1998
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Application #:
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08937528
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Filing Dt:
|
09/25/1997
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Title:
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FLOATING BITLINE TEST MODE WITH DIGITALLY CONTROLLABLE BITLINE EQUALIZERS
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Patent #:
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|
Issue Dt:
|
06/20/2000
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Application #:
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08937570
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Filing Dt:
|
09/25/1997
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Title:
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SEMICONDUCTOR MEMORY HAVING REDUNDANCY CIRCUIT
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Patent #:
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|
Issue Dt:
|
09/28/1999
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Application #:
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08937571
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Filing Dt:
|
09/25/1997
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Title:
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A METHOD AND APPARATUS FOR REDUCING THE BIAS CURRENT IN A REFERENCE VOLTAGE CIRCUIT
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Patent #:
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|
Issue Dt:
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09/21/1999
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Application #:
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08937572
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Filing Dt:
|
09/25/1997
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Title:
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METHOD OF END POINT DETECTION USING A SINUSOIDAL INTERFERENCE SIGNAL FOR A WET ETCH PROCESS
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Patent #:
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Issue Dt:
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10/24/2000
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Application #:
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08937781
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Filing Dt:
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09/25/1997
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Title:
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METHOD OF FABRICATING SEMICONDUCTOR CHIPS WITH SILICIDE AND IMPLANTED JUNCTIONS
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Patent #:
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Issue Dt:
|
04/04/2000
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Application #:
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08938072
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Filing Dt:
|
09/26/1997
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Title:
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METALIZATION SYSTEM HAVING AN ENHANCED THERMAL CONDUCTIVITY
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Patent #:
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Issue Dt:
|
03/02/1999
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Application #:
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08938073
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Filing Dt:
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09/26/1997
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Title:
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SPACE-EFFICIENT MDQ SWITCH PLACEMENT
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Patent #:
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Issue Dt:
|
11/03/1998
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Application #:
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08938074
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Filing Dt:
|
09/26/1997
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Title:
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SEMICONDUCTOR MEMORY HAVING SPACE-EFFICIENT LAYOUT
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Patent #:
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Issue Dt:
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01/11/2000
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Application #:
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08938196
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Filing Dt:
|
09/26/1997
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Title:
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BUFFER LAYER FOR IMPROVING CONTROL OF LAYER THICKNESS
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Patent #:
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|
Issue Dt:
|
08/10/1999
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Application #:
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08939148
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Filing Dt:
|
09/29/1997
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Title:
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DEPOSITION OF CARBON INTO NITRIDE LAYER FOR IMPROVED SELECTIVITY OF OXIDE TO NITRIDE ETCHRATE FOR SELF ALIGNED CONTACT ETCHING
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|
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Patent #:
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|
Issue Dt:
|
11/02/1999
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Application #:
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08939208
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Filing Dt:
|
09/29/1997
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Title:
|
MULTI-LEVEL CONDUCTIVE STRUCTURE INCLUDING LOW CAPACITANCE MATERIAL
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|
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Patent #:
|
|
Issue Dt:
|
02/02/1999
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Application #:
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08939216
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Filing Dt:
|
09/29/1997
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Title:
|
TECHNIQUES FOR ETCHING A SILICON DIOXIDE-CONTAINING LAYER
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|
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Patent #:
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|
Issue Dt:
|
09/15/1998
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Application #:
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08939547
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Filing Dt:
|
09/29/1997
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Title:
|
APPARATUS AND METHOD FOR IMPROVED WASHING AND DRYING OF SEMICONDUCTOR WAFERS
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|
|
Patent #:
|
|
Issue Dt:
|
05/25/1999
|
Application #:
|
08940233
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Filing Dt:
|
09/30/1997
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Title:
|
REDUCTION OF PAD EROSION
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|
|
Patent #:
|
|
Issue Dt:
|
04/23/2002
|
Application #:
|
08940235
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Filing Dt:
|
09/30/1997
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Title:
|
RELIABLE POLICIDE GATE STACK WITH REDUCED SHEET RESISTANCE AND THICKNESS
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|
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Patent #:
|
|
Issue Dt:
|
01/16/2001
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Application #:
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08940236
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Filing Dt:
|
09/30/1997
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Title:
|
SPACERS TO BLOCK DEEP JUNCTION IMPLANTS AND SILICIDE FORMATION IN INTEGRATED CIRCUITS
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|
|
Patent #:
|
|
Issue Dt:
|
11/09/1999
|
Application #:
|
08940237
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Filing Dt:
|
09/30/1997
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Title:
|
REDUCED PARASITIC LEAKAGE IN SEMICONDUCTOR DEVICES
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|
|
Patent #:
|
|
Issue Dt:
|
03/09/1999
|
Application #:
|
08940650
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Filing Dt:
|
09/30/1997
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Title:
|
PLANARIZATION OF A NON-CONFORMAL DEVICE LAYER IN SEMICONDUCTOR FABRICATION
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|
|
Patent #:
|
|
Issue Dt:
|
05/15/2001
|
Application #:
|
08940806
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Filing Dt:
|
09/30/1997
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Title:
|
METHODS FOR PERFORMING PLANARIZATION AND RECESS ETCHES AND APPARATUS THEREFOR
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|
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Patent #:
|
|
Issue Dt:
|
10/03/2000
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Application #:
|
08940807
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Filing Dt:
|
09/30/1997
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Title:
|
SOFT PASSIVATION LAYER IN SEMICONDUCTOR FABRICATION
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Patent #:
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|
Issue Dt:
|
07/13/1999
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Application #:
|
08940861
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Filing Dt:
|
09/29/1997
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Title:
|
SPACE-EFFICIENT SEMICONDUCTOR MEMORY HAVING HIERARCHICAL COLUMN SELECT LINE ARCHITECTURE
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|
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Patent #:
|
|
Issue Dt:
|
08/17/1999
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Application #:
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08940862
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Filing Dt:
|
09/29/1997
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Title:
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CONSTANT CURRENT CMOS OUTPUT DRIVER CIRCUIT WITH DUAL GATE TRANSISTOR DEVICES
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|
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Patent #:
|
|
Issue Dt:
|
02/01/2000
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Application #:
|
08940891
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Filing Dt:
|
09/30/1997
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Title:
|
HARD ETCH MASK
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|
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Patent #:
|
|
Issue Dt:
|
06/06/2000
|
Application #:
|
08940892
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Filing Dt:
|
09/30/1997
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Title:
|
METHOD FOR PATTERNING INTEGRATED CIRCUIT CONDUCTORS
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|
|
Patent #:
|
|
Issue Dt:
|
05/23/2000
|
Application #:
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08940895
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Filing Dt:
|
09/30/1997
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Title:
|
DUAL DAMASCENE PROCESS FOR METAL LAYERS AND ORGANIC INTERMETAL LAYERS
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|
|
Patent #:
|
|
Issue Dt:
|
08/24/1999
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Application #:
|
08940899
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Filing Dt:
|
09/30/1997
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Title:
|
POWER-ON DETECTION AND ENABLING CIRCUIT WITH VERY FAST DETECTION OF POWER-OFF
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|
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Patent #:
|
|
Issue Dt:
|
09/21/1999
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Application #:
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08941093
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Filing Dt:
|
09/30/1997
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Title:
|
ENDPOINT DETECTION METHOD AND APPARATUS
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|
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Patent #:
|
|
Issue Dt:
|
07/18/2000
|
Application #:
|
08941600
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Filing Dt:
|
09/30/1997
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Title:
|
REDUCTION OF GATE-INDUCED DRAIN LEAKAGE IN SEMICONDUCTOR DEVICES
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|
|
Patent #:
|
|
Issue Dt:
|
08/01/2000
|
Application #:
|
08942273
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Filing Dt:
|
09/30/1997
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Title:
|
GAPFILL OF SEMICONDUCTOR STRUCTURE USING DOPED SILICATE GLASSES
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|
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Patent #:
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|
Issue Dt:
|
10/12/1999
|
Application #:
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08942275
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Filing Dt:
|
09/30/1997
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Title:
|
SEMICONDUCTOR MEMORY HAVING HIERARCHICAL BIT LINE ARCHITECTURE WITH NON-UNIFORM LOCAL BIT LINES
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|
|
Patent #:
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|
Issue Dt:
|
01/26/1999
|
Application #:
|
08943080
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Filing Dt:
|
10/01/1997
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Title:
|
FERROMAGNETIC MEMORY USING SOFT MAGNETIC MATERIAL AND HARD MAGNETIC MATERIAL
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|
|
Patent #:
|
|
Issue Dt:
|
02/02/1999
|
Application #:
|
08943910
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Filing Dt:
|
09/30/1997
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Title:
|
REDUCING OXIDATION STRESS IN THE FABRICATION OF DEVICES
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|
|
Patent #:
|
|
Issue Dt:
|
12/19/2000
|
Application #:
|
08978354
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Filing Dt:
|
11/25/1997
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Title:
|
MASK BLANK AND METHOD OF PRODUCING MASK
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|
|
Patent #:
|
|
Issue Dt:
|
01/18/2000
|
Application #:
|
08992378
|
Filing Dt:
|
12/17/1997
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Title:
|
MEMORY WITH WORD LINE VOLTAGE CONTROL
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|
|
Patent #:
|
|
Issue Dt:
|
12/08/1998
|
Application #:
|
08992379
|
Filing Dt:
|
12/17/1997
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Title:
|
MEMORY ARRAY WITH REDUCED CHARGING CURRENT
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|
|
Patent #:
|
|
Issue Dt:
|
06/29/1999
|
Application #:
|
08993537
|
Filing Dt:
|
12/18/1997
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Title:
|
SEMICONDUCTOR MEMORY HAVING HIERARCHICAL BIT LINE ARCHITECTURE WITH INTERLEAVED MASTER BITLINES
|
|
|
Patent #:
|
|
Issue Dt:
|
05/30/2000
|
Application #:
|
08993538
|
Filing Dt:
|
12/18/1997
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Title:
|
SEMICONDUCTOR MEMORY HAVING HIERARCHICAL BIT LINE AND/OR WORD LINE ARCHITECTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/07/1999
|
Application #:
|
08993743
|
Filing Dt:
|
12/19/1997
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Title:
|
METHOD OF FORMING DOPANT OUTDIFFUSION CONTROL STRUCTURE INCLUDING SELECTIVELY GROWN SILICON NITRIDE IN A TRENCH CAPACITOR OF A DRAM CELL
|
|
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Patent #:
|
|
Issue Dt:
|
02/16/1999
|
Application #:
|
08996576
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Filing Dt:
|
12/23/1997
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Title:
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METHOD AND APPARATUS FOR DETERMINING WAFER WARPAGE FOR OPTIMIZED ELECTROSTATIC CHUCK CLAMPING VOLTAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/11/1999
|
Application #:
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08997460
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Filing Dt:
|
12/23/1997
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Title:
|
METHOD FOR DETECTING UNDERETCHED VIAS
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|
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Patent #:
|
|
Issue Dt:
|
03/07/2000
|
Application #:
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08997682
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Filing Dt:
|
12/23/1997
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Title:
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DUAL DAMASCENE WITH BOND PADS
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|
|
Patent #:
|
|
Issue Dt:
|
09/26/2000
|
Application #:
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08998856
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Filing Dt:
|
12/29/1997
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Title:
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REDUCED PAD EROSION
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Patent #:
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Issue Dt:
|
02/02/1999
|
Application #:
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08998857
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Filing Dt:
|
12/29/1997
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Title:
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WAFER SURFACE CLEANING APPARATUS AND METHOD
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Patent #:
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Issue Dt:
|
03/07/2000
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Application #:
|
08998858
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Filing Dt:
|
12/29/1997
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Title:
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REDUCTION OF BLACK SILICON IN SEMICONDUCTOR FABRICATION
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Patent #:
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Issue Dt:
|
05/16/2000
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Application #:
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08999926
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Filing Dt:
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06/23/1997
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Title:
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CONTROL OF CRITICAL DIMENSIONS THROUGH MEASUREMENT OF ABOSRBED RADIATION
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Patent #:
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|
Issue Dt:
|
10/19/1999
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Application #:
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09000625
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Filing Dt:
|
12/30/1997
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Title:
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REDUCED STAND BY POWER CONSUMPTION IN A DRAM
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Patent #:
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|
Issue Dt:
|
11/01/2005
|
Application #:
|
09000626
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Filing Dt:
|
12/30/1997
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Title:
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RECESSED SHALLOW TRENCH ISOLATION STRUCTURE NITRIDE LINER AND METHOD FOR MAKING SAME
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|
Patent #:
|
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Issue Dt:
|
12/11/2001
|
Application #:
|
09030227
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Filing Dt:
|
02/25/1998
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Title:
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CONTACT BETWEEN A MONOCRYSTALLINE SILICON REGION AND A POLYCRYSTALLINE SILICON STRUCTURE AND METHOD FOR PRODUCING SUCH A CONTACT
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Patent #:
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Issue Dt:
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05/30/2000
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Application #:
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09030406
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Filing Dt:
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02/25/1998
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Title:
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METHOD FOR PRODUCING A POLYCRYSTALLINE SILICON STRUCTURE AND POLYCRYSTALLINE SILICON LAYER TO BE PRODUCED BY THE METHOD
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Patent #:
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Issue Dt:
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06/20/2000
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Application #:
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09049699
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Filing Dt:
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03/27/1998
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Title:
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METHOD AND APPARATUS FOR SIZE OPTIMIZATION OF STORAGE UNITS
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Patent #:
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Issue Dt:
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08/10/1999
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Application #:
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09095985
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Filing Dt:
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06/11/1998
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Title:
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APPARATUS AND METHOD FOR IMPROVED WASHING AND DRYING OF SEMICONDUCTOR WAFERS
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Patent #:
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Issue Dt:
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10/07/2003
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Application #:
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09137179
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Filing Dt:
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08/20/1998
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Title:
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ETCHING COMPOSITION AND USE THEREOF
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Patent #:
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Issue Dt:
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08/17/1999
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Application #:
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09183246
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Filing Dt:
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10/30/1998
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Title:
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RECESSED SHALLOW TRENCH ISOLATION STRUCTURE NITRIDE LINER AND METHOD FOR MAKING SAME
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Patent #:
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Issue Dt:
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11/30/1999
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Application #:
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09187153
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Filing Dt:
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11/06/1998
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Title:
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APPARATUS FOR CONTROLLING CIRCUIT RESPONSE DURING POWER-UP
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Patent #:
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Issue Dt:
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12/14/1999
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Application #:
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09187165
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Filing Dt:
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11/06/1998
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Title:
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PLANARIZATION OF A NON-CONFORMAL DEVICE LAYER IN SEMICONDUCTOR FABRICATION
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Patent #:
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Issue Dt:
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10/05/1999
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Application #:
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09197360
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Filing Dt:
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11/20/1998
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Title:
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ANTISENSE MODULATION OF INHIBITOR-KAPPA B KINASE-ALPHA EXPRESSION
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Patent #:
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Issue Dt:
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04/02/2002
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Application #:
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09197371
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Filing Dt:
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11/20/1998
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Title:
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PLASTIC COMPOSITIONS FOR SHEATHING A METAL OR SEMICONDUCTOR BODY
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Patent #:
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Issue Dt:
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12/19/2000
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Application #:
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09215011
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Filing Dt:
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12/17/1998
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Title:
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REDUCED PARASITIC LEAKAGE IN SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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08/01/2000
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Application #:
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09228610
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Filing Dt:
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01/12/1999
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Title:
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AN ADJUSTABLE DELAY CIRCUIT
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Patent #:
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Issue Dt:
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11/14/2000
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Application #:
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09228611
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Filing Dt:
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01/12/1999
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Title:
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DRAM CELL ARRANGEMENT AND METHOD FOR ITS PRODUCTION
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|
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Patent #:
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Issue Dt:
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01/21/2003
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Application #:
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09232081
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Filing Dt:
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01/15/1999
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Title:
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TRENCH CAPACITOR WITH INSULATION COLLAR AND METHOD FOR PRODUCING THE TRENCH CAPACITOR
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Patent #:
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Issue Dt:
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11/30/1999
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Application #:
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09232083
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Filing Dt:
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01/15/1999
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Title:
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MEMORY CELL CONFIGURATION AND METHOD FOR ITS FABRICATION
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Patent #:
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Issue Dt:
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04/10/2001
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Application #:
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09243296
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Filing Dt:
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02/02/1999
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Title:
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INTEGRATED MEMORY
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|
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Patent #:
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Issue Dt:
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07/10/2001
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Application #:
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09250362
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Filing Dt:
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02/12/1999
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Title:
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MEMORY CELL CONFIGURATION AND CORRESPONDING FABRICATION METHOD
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|
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Patent #:
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Issue Dt:
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03/19/2002
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Application #:
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09250516
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Filing Dt:
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02/16/1999
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Title:
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CIRCUIT ARRANGEMENT WITH AT LEAST ONE CAPACITOR
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Patent #:
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Issue Dt:
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11/30/1999
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Application #:
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09251611
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Filing Dt:
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02/17/1999
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Title:
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SEMICONDUCTOR WAFER TEMPERATURE MEASUREMENT AND CONTROL THEREOF USING GAS TEMPERATURE MEASUREMENT
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Patent #:
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Issue Dt:
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02/22/2000
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Application #:
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09258940
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Filing Dt:
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03/01/1999
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Title:
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INTEGRATED MEMORY
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|
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Patent #:
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Issue Dt:
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06/04/2002
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Application #:
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09261100
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Filing Dt:
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03/02/1999
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Title:
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INTEGRATED CIRCUIT AND METHOD FOR TESTING IT
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Patent #:
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Issue Dt:
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08/01/2000
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Application #:
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09272077
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Filing Dt:
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03/18/1999
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Title:
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DRAM CELL ARRANGEMENT
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Patent #:
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Issue Dt:
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08/28/2001
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Application #:
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09272968
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Filing Dt:
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03/19/1999
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Title:
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MOS TRANSISTOR IN A SINGLE-TRANSISTOR MEMORY CELL HAVING A LOCALLY THICKENED GATE OXIDE, AND PRODUCTION PROCESS
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Patent #:
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Issue Dt:
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03/28/2000
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Application #:
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09273648
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Filing Dt:
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03/23/1999
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Title:
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METHOD FOR PROGRAMMING A ROM CELL ARRANGEMENT
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