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Reel/Frame:024120/0505   Pages: 30
Recorded: 02/18/2010
Attorney Dkt #:609612800100
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 159
Page 2 of 2
Pages: 1 2
1
Patent #:
6698086
Issue Dt:
03/02/2004
Application #:
09163874
Filing Dt:
09/30/1998
Title:
METHOD FOR THE LINEAR CONFIGURATION OF METALLIC FUSE SECTIONS ON WAFERS
2
Patent #:
6156673
Issue Dt:
12/05/2000
Application #:
09164115
Filing Dt:
09/30/1998
Title:
PROCESS FOR PRODUCING A CERAMIC LAYER
3
Patent #:
6126998
Issue Dt:
10/03/2000
Application #:
09164119
Filing Dt:
09/30/1998
Title:
PROCESS FOR PRODUCING A CERAMIC LAYER CONTAINING BI
4
Patent #:
6189059
Issue Dt:
02/13/2001
Application #:
09170184
Filing Dt:
10/13/1998
Title:
COMMUNICATIONS SYSTEM WITH A MASTER STATION AND AT LEAST ONE SLAVE STATION
5
Patent #:
6441424
Issue Dt:
08/27/2002
Application #:
09176558
Filing Dt:
10/21/1998
Title:
INTEGRATED CIRCUIT CONFIGURATION HAVING AT LEAST ONE CAPACITOR AND METHOD FOR PRODUCING THE SAME
6
Patent #:
6028803
Issue Dt:
02/22/2000
Application #:
09180665
Filing Dt:
11/12/1998
Title:
READ AMPLIFIER FOR SEMICONDUCTOR MEMORY CELLS WITH MEANS TO COMPENSATE THRESHOLD VOLTAGE DIFFERENCES IN READ AMPLIFIER TRANSISTORS
7
Patent #:
5977589
Issue Dt:
11/02/1999
Application #:
09191482
Filing Dt:
11/13/1998
Title:
DRAM CELL ARRANGEMENT AND METHOD FOR THE PRODUCTION THEREOF
8
Patent #:
6445091
Issue Dt:
09/03/2002
Application #:
09197369
Filing Dt:
11/20/1998
Title:
INTEGRATED SEMICONDUCTOR CIRCUIT HAVING AT LEAST TWO SUPPLY NETWORKS
9
Patent #:
6015988
Issue Dt:
01/18/2000
Application #:
09197391
Filing Dt:
11/20/1998
Title:
MICROSTRUCTURE AND METHODS FOR FABRICATING SUCH STRUCTURE
10
Patent #:
6038164
Issue Dt:
03/14/2000
Application #:
09200071
Filing Dt:
11/25/1998
Title:
SRAM CELL CONFIGURATION AND METHOD FOR ITS FABRICATION
11
Patent #:
6171755
Issue Dt:
01/09/2001
Application #:
09201728
Filing Dt:
11/30/1998
Title:
CHEMICALLY AMPLIFIED RESIST
12
Patent #:
6583464
Issue Dt:
06/24/2003
Application #:
09201733
Filing Dt:
11/30/1998
Title:
MEMORY CELL USING AMORPHOUS MATERIAL TO STABILIZE THE BOUNDARY FACE BETWEEN POLYCHRYSTALLINE SEMICONDUCTOR MATERIAL OF A CAPACITOR AND MONCRYSTALLINE SEMICONDUCTOR MATERIAL OF A TRANSISTOR
13
Patent #:
5986952
Issue Dt:
11/16/1999
Application #:
09204927
Filing Dt:
12/03/1998
Title:
REDUNDANCY CONCEPT FOR MEMORY CIRCUITS HAVING ROM MEMORY CELLS
14
Patent #:
6229169
Issue Dt:
05/08/2001
Application #:
09213724
Filing Dt:
12/17/1998
Title:
MEMORY CELL CONFIGURATION, METHOD FOR FABRICATING IT AND METHODS FOR OPERATING IT
15
Patent #:
6614100
Issue Dt:
09/02/2003
Application #:
09220745
Filing Dt:
12/23/1998
Title:
LEAD FRAME FOR THE INSTALLATION OF AN INTEGRATED CIRCUIT IN AN INJECTION-MOLDED PACKAGE
16
Patent #:
6057595
Issue Dt:
05/02/2000
Application #:
09221774
Filing Dt:
12/28/1998
Title:
INTEGRATED SEMICONDUCTOR CIRCUIT HOUSING
17
Patent #:
6140177
Issue Dt:
10/31/2000
Application #:
09242153
Filing Dt:
02/09/1999
Title:
PROCESS FOR MANUFACTURING A CAPACITOR IN A SEMICONDUCTOR ARRANGEMENT INCLUDING FORMING A STATISTICAL HSG MASK OF SILICON AND GERMANIUM NUCLEI
18
Patent #:
6218727
Issue Dt:
04/17/2001
Application #:
09246745
Filing Dt:
02/08/1999
Title:
WAFER FRAME
19
Patent #:
6355954
Issue Dt:
03/12/2002
Application #:
09251616
Filing Dt:
02/17/1999
Title:
DEVICE WITH ASYMMETRICAL CHANNEL DOPANT PROFILE
20
Patent #:
6037209
Issue Dt:
03/14/2000
Application #:
09254696
Filing Dt:
03/15/1999
Title:
METHOD FOR PRODUCING A DRAM CELLULAR ARRANGEMENT
21
Patent #:
5981302
Issue Dt:
11/09/1999
Application #:
09256048
Filing Dt:
02/23/1999
Title:
INTEGRATED MULTI-LAYER TEST PADS AND METHODS THEREFOR
22
Patent #:
6200851
Issue Dt:
03/13/2001
Application #:
09272217
Filing Dt:
03/18/1999
Title:
MEMORY CELL THAT INCLUDES A VERTICAL TRANSISTOR AND A TRENCH CAPACITOR
23
Patent #:
6150210
Issue Dt:
11/21/2000
Application #:
09272218
Filing Dt:
03/18/1999
Title:
MEMORY CELL THAT INCLUDES A VERTICAL TRANSISTOR AND A TRENCH CAPACITOR
24
Patent #:
6573593
Issue Dt:
06/03/2003
Application #:
09272668
Filing Dt:
03/18/1999
Title:
INTEGRATED CIRCUIT WITH A HOUSING ACCOMMODATING THE INTEGRATED CIRCUIT
25
Patent #:
6168988
Issue Dt:
01/02/2001
Application #:
09281691
Filing Dt:
03/30/1999
Title:
METHOD FOR PRODUCING BARRIER-FREE SEMICONDUCTOR MEMORY CONFIGURATIONS
26
Patent #:
6627934
Issue Dt:
09/30/2003
Application #:
09281696
Filing Dt:
03/30/1999
Title:
INTEGRATED SEMICONDUCTOR MEMORY CONFIGURATION WITH A BURIED PLATE ELECTRODE AND METHOD FOR ITS FABRICATION
27
Patent #:
6197633
Issue Dt:
03/06/2001
Application #:
09281822
Filing Dt:
03/30/1999
Title:
METHOD FOR THE PRODUCTION OF AN INTEGRATED SEMICONDUCTOR MEMORY CONFIGURATION
28
Patent #:
6097050
Issue Dt:
08/01/2000
Application #:
09282041
Filing Dt:
03/30/1999
Title:
MEMORY CONFIGURATION WITH SELF-ALIGNING NON-INTEGRATED CAPACITOR CONFIGURATION
29
Patent #:
6346424
Issue Dt:
02/12/2002
Application #:
09282094
Filing Dt:
03/30/1999
Title:
PROCESS FOR PRODUCING HIGH-EPSILON DIELECTRIC LAYER OR FERROELECTRIC LAYER
30
Patent #:
6297526
Issue Dt:
10/02/2001
Application #:
09282097
Filing Dt:
03/30/1999
Title:
PROCESS FOR PRODUCING BARRIER-FREE SEMICONDUCTOR MEMORY CONFIGURATIONS
31
Patent #:
6043529
Issue Dt:
03/28/2000
Application #:
09282099
Filing Dt:
03/30/1999
Title:
SEMICONDUCTOR CONFIGURATION WITH A PROTECTED BARRIER FOR A STACKED CELL
32
Patent #:
6274431
Issue Dt:
08/14/2001
Application #:
09301108
Filing Dt:
04/28/1999
Title:
METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT ARRANGEMENT HAVING AT LEAST ONE MOS TRANSISTOR
33
Patent #:
6285621
Issue Dt:
09/04/2001
Application #:
09373476
Filing Dt:
08/12/1999
Title:
METHOD OF MINIMIZING THE ACCESS TIME IN SEMICONDUCTOR MEMORIES
34
Patent #:
6096921
Issue Dt:
08/01/2000
Application #:
09388274
Filing Dt:
09/01/1999
Title:
O-AMINO(THIO) PHENOLCARBOXYLIC ACIDS, AND THEIR PREPARATION
35
Patent #:
6115286
Issue Dt:
09/05/2000
Application #:
09392767
Filing Dt:
09/07/1999
Title:
DATA MEMORY
36
Patent #:
6158029
Issue Dt:
12/05/2000
Application #:
09395320
Filing Dt:
09/13/1999
Title:
METHOD OF TESTING AN INTEGRATED CIRCUIT HAVING A MEMORY AND A TEST CIRCUIT
37
Patent #:
6137314
Issue Dt:
10/24/2000
Application #:
09450403
Filing Dt:
11/29/1999
Title:
INPUT CIRCUIT FOR AN INTEGRATED CIRCUIT
38
Patent #:
6279129
Issue Dt:
08/21/2001
Application #:
09465726
Filing Dt:
12/17/1999
Title:
CONFIGURATION OF MEMORY CELLS AND METHOD OF CHECKING THE OPERATION OF MEMORY CELLS
39
Patent #:
6337247
Issue Dt:
01/08/2002
Application #:
09487411
Filing Dt:
01/18/2000
Title:
Method of producing a vertical mos transistor
40
Patent #:
6261382
Issue Dt:
07/17/2001
Application #:
09495795
Filing Dt:
02/01/2000
Title:
Wafer marking
41
Patent #:
6395454
Issue Dt:
05/28/2002
Application #:
09498532
Filing Dt:
02/04/2000
Title:
Integrated electrical circuit with passivation layer
42
Patent #:
6389086
Issue Dt:
05/14/2002
Application #:
09521396
Filing Dt:
03/08/2000
Title:
Digital circuit having a filter unit for suppressing glitches
43
Patent #:
6490190
Issue Dt:
12/03/2002
Application #:
09528159
Filing Dt:
03/17/2000
Title:
MEMORY CELL CONFIGURATION, MAGNETIC RAM, AND ASSOCIATIVE MEMORY
44
Patent #:
6417043
Issue Dt:
07/09/2002
Application #:
09528268
Filing Dt:
03/17/2000
Title:
MEMORY CELL CONFIGURATION AND FABRICATION METHOD
45
Patent #:
6191985
Issue Dt:
02/20/2001
Application #:
09528424
Filing Dt:
03/17/2000
Title:
Dynamic memory having two modes of operation
46
Patent #:
6208562
Issue Dt:
03/27/2001
Application #:
09536029
Filing Dt:
03/27/2000
Title:
Digital memory and method of operation for a digital memory
47
Patent #:
6410407
Issue Dt:
06/25/2002
Application #:
09539235
Filing Dt:
03/30/2000
Title:
PRODUCT INCLUDING A SILICON-CONTAINING FUNCTIONAL LAYER AND AN INSULATING LAYER MADE OF SILICON DIOXIDE, AND METHOD FABRICATING THE PRODUCT
48
Patent #:
6468348
Issue Dt:
10/22/2002
Application #:
09539237
Filing Dt:
03/30/2000
Title:
METHOD OF PRODUCING AN OPEN FORM
49
Patent #:
6351408
Issue Dt:
02/26/2002
Application #:
09544761
Filing Dt:
04/06/2000
Title:
Memory cell configuration
50
Patent #:
6345372
Issue Dt:
02/05/2002
Application #:
09547683
Filing Dt:
04/12/2000
Title:
Method for testing bus connections of writable and readable integrated electronic circuits, in particular memory components
51
Patent #:
7064439
Issue Dt:
06/20/2006
Application #:
09595860
Filing Dt:
06/16/2000
Title:
INTEGRATED CIRCUIT HAVING A DIFFUSION BLOCKER CONFIGURED AS A BLOCKER LAYER AND CONNECTION PIECES COMPOSED OF ALUMINUM COVERING CONTACT HOLES AND METHODS FOR FABRICATING THE SAME
52
Patent #:
RE37930
Issue Dt:
12/10/2002
Application #:
09677368
Filing Dt:
01/08/2001
Title:
DRAM INCLUDING AN ADDRESS SPACE DIVIDED INTO INDIVIDUAL BLOCKS HAVING MEMORY CELLS ACTIVATED BY ROW ADDRESS SIGNALS
53
Patent #:
6274410
Issue Dt:
08/14/2001
Application #:
09729068
Filing Dt:
12/04/2000
Publication #:
US20010000758
Pub Dt:
05/03/2001
Title:
Method of programming a semiconductor memory
54
Patent #:
6420228
Issue Dt:
07/16/2002
Application #:
09851051
Filing Dt:
05/08/2001
Title:
METHOD FOR THE PRODUCTION OF A DRAM CELL CONFIGURATION
55
Patent #:
6605505
Issue Dt:
08/12/2003
Application #:
09883011
Filing Dt:
06/15/2001
Publication #:
US20010039106
Pub Dt:
11/08/2001
Title:
PROCESS FOR PRODUCING AN INTEGRATED SEMICONDUCTOR MEMORY CONFIGURATION
56
Patent #:
6479373
Issue Dt:
11/12/2002
Application #:
09884188
Filing Dt:
06/19/2001
Publication #:
US20020016044
Pub Dt:
02/07/2002
Title:
METHOD OF STRUCTURING LAYERS WITH A POLYSILICON LAYER AND AN OVERLYING METAL OR METAL SILICIDE LAYER USING A THREE STEP ETCHING PROCESS WITH FLUORINE, CHLORINE, BROMINE CONTAINING GASES
57
Patent #:
6437178
Issue Dt:
08/20/2002
Application #:
09901218
Filing Dt:
07/09/2001
Publication #:
US20010056203
Pub Dt:
12/27/2001
Title:
O-AMINOPHENOLCARBOXYLIC ACID AND O-AMINOTHIOPHENOLCARBOXYLIC ACID
58
Patent #:
6566202
Issue Dt:
05/20/2003
Application #:
10081902
Filing Dt:
02/22/2002
Publication #:
US20020094628
Pub Dt:
07/18/2002
Title:
INTEGRATED CIRCUIT HAVING AT LEAST TWO VERTICAL MOS TRANSISTORS AND METHOD FOR MANUFACTURING SAME
59
Patent #:
6693022
Issue Dt:
02/17/2004
Application #:
10226764
Filing Dt:
08/23/2002
Publication #:
US20030017684
Pub Dt:
01/23/2003
Title:
CVD METHOD OF PRODUCING IN SITU-DOPED POLYSILICON LAYERS AND POLYSILICON LAYERED STRUCTURES
Assignor
1
SIEMENS AKTIENGESELLSCHAFT
Exec Dt:
03/31/1999
Assignee
1
INFINEON TECHNOLOGIES AG
ST.-MARTIN-STR. 53
MUNICH, GERMANY 81541
Correspondence name and address
JONATHAN BOCKMAN
C/O MORRISON AND FOERSTER LLP
1650 TYSONS BLVD. SUITE 400
MCLEAN, VIRGINIA 22102

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