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Reel/Frame:024170/0300   Pages: 12
Recorded: 04/01/2010
Conveyance: CHANGE OF NAME (SEE DOCUMENT FOR DETAILS).
Total properties: 142
Page 1 of 2
Pages: 1 2
1
Patent #:
5821800
Issue Dt:
10/13/1998
Application #:
08799074
Filing Dt:
02/11/1997
Title:
HIGH-VOLTAGE CMOS LEVEL SHIFTER
2
Patent #:
5801579
Issue Dt:
09/01/1998
Application #:
08808237
Filing Dt:
02/28/1997
Title:
HIGH VOLTAGE NMOS PASS GATE FOR INTEGRATED CIRCUIT WITH HIGH VOLTAGE GENERATOR
3
Patent #:
5912489
Issue Dt:
06/15/1999
Application #:
08940674
Filing Dt:
09/30/1997
Title:
A DUAL SOURCE SIDE POLYSILICON SELECT GATE STRUCTURE UTILIZING SINGLE TUNNEL OXIDE FOR NAND ARRAY FLASH MEMORY
4
Patent #:
5999452
Issue Dt:
12/07/1999
Application #:
09063688
Filing Dt:
04/21/1998
Title:
DUAL SOURCE SIDE POLYSILICON SELECT GATE STRUCTURE AND PROGRAMMING METHOD UTILIZING SINGLE TUNNEL OXIDE FOR NAND ARRAY FLASH MEMORY
5
Patent #:
6159795
Issue Dt:
12/12/2000
Application #:
09109664
Filing Dt:
07/02/1998
Title:
LOW VOLTAGE JUNCTION AND HIGH VOLTAGE JUNCTION OPTIMIZATION FOR FLASH MEMORY
6
Patent #:
6346737
Issue Dt:
02/12/2002
Application #:
09109755
Filing Dt:
07/02/1998
Title:
SHALLOW TRENCH ISOLATION PROCESS PARTICULARLY SUITED FOR HIGH VOLTAGE CIRCUITS
7
Patent #:
6100754
Issue Dt:
08/08/2000
Application #:
09128024
Filing Dt:
08/03/1998
Title:
VT REFERENCE VOLTAGE FOR EXTREMELY LOW POWER SUPPLY
8
Patent #:
6033955
Issue Dt:
03/07/2000
Application #:
09159023
Filing Dt:
09/23/1998
Title:
METHOD OF MAKING FLEXIBLY PARTITIONED METAL LINE SEGMENTS FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE WITH A FLEXIBLE BANK PARTITION ARCHITECTURE
9
Patent #:
6005803
Issue Dt:
12/21/1999
Application #:
09159342
Filing Dt:
09/23/1998
Title:
MEMORY ADDRESS DECODING CIRCUIT FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE WITH A FLEXIBLE BANK PARTITION ARCHITECTURE
10
Patent #:
6275894
Issue Dt:
08/14/2001
Application #:
09159489
Filing Dt:
09/23/1998
Title:
BANK SELECTOR CIRCUIT FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE WITH A FLEXIBLE BANK PARTITION ARCHITECTURE
11
Patent #:
6134146
Issue Dt:
10/17/2000
Application #:
09166385
Filing Dt:
10/05/1998
Title:
WORDLINE DRIVER FOR FLASH ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY (EEPROM)
12
Patent #:
5995417
Issue Dt:
11/30/1999
Application #:
09175646
Filing Dt:
10/20/1998
Title:
SCHEME FOR PAGE ERASE AND ERASE VERIFY IN A NON -VOLATILE MEMORY ARRAY
13
Patent #:
5978267
Issue Dt:
11/02/1999
Application #:
09175647
Filing Dt:
10/20/1998
Title:
BIT LINE BIASING METHOD TO ELIMATE PROGRAM DISTURBANCE IN A NON-VOLATILE MEMORY DEVICE AND MEMORY DEVICE EMPLOYING THE SAME
14
Patent #:
6143608
Issue Dt:
11/07/2000
Application #:
09283308
Filing Dt:
03/31/1999
Title:
BARRIER LAYER DECREASES NITROGEN CONTAMINATION OF PERIPHERAL GATE REGIONS DURING TUNNEL OXIDE NITRIDATION
15
Patent #:
6228782
Issue Dt:
05/08/2001
Application #:
09309994
Filing Dt:
05/11/1999
Title:
CORE FIELD ISOLATION FOR A NAND FLASH MEMORY
16
Patent #:
6266275
Issue Dt:
07/24/2001
Application #:
09410512
Filing Dt:
09/30/1999
Title:
DUAL SOURCE SIDE POLYSILICON SELECT GATE STRUCTURE AND PROGRAMMING METHOD UTILIZING SINGLE TUNNEL OXIDE FOR NAND ARRAY FLASH MEMORY
17
Patent #:
6147906
Issue Dt:
11/14/2000
Application #:
09419695
Filing Dt:
10/14/1999
Title:
METHOD AND SYSTEM FOR SAVING OVERHEAD PROGRAM TIME IN A MEMORY DEVICE
18
Patent #:
6125055
Issue Dt:
09/26/2000
Application #:
09421105
Filing Dt:
10/19/1999
Title:
SECTOR WRITE PROTECT CAMS FOR A SIMULTANEOUS OPERATION FLASH MEMORY
19
Patent #:
6201753
Issue Dt:
03/13/2001
Application #:
09421142
Filing Dt:
10/19/1999
Title:
LATCHING CAM DATA IN A FLASH MEMORY DEVICE
20
Patent #:
6550028
Issue Dt:
04/15/2003
Application #:
09421470
Filing Dt:
10/19/1999
Title:
ARRAY VT MODE IMPLEMENTATION FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
21
Patent #:
6285585
Issue Dt:
09/04/2001
Application #:
09421471
Filing Dt:
10/19/1999
Title:
OUTPUT SWITCHING IMPLEMENTATION FOR A FLASH MEMORY DEVICE
22
Patent #:
6331950
Issue Dt:
12/18/2001
Application #:
09421757
Filing Dt:
10/19/1999
Title:
WRITE PROTECT INPUT IMPLEMENTATION FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
23
Patent #:
6571307
Issue Dt:
05/27/2003
Application #:
09421758
Filing Dt:
10/19/1999
Title:
MULTIPLE PURPOSE BUS FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
24
Patent #:
6163478
Issue Dt:
12/19/2000
Application #:
09421774
Filing Dt:
10/19/1999
Title:
COMMON FLASH INTERFACE IMPLEMENTATION FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
25
Patent #:
6327181
Issue Dt:
12/04/2001
Application #:
09421775
Filing Dt:
10/19/1999
Title:
REFERENCE CELL BITLINE PATH ARCHITECTURE FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
26
Patent #:
6111787
Issue Dt:
08/29/2000
Application #:
09421776
Filing Dt:
10/19/1999
Title:
ADDRESS TRANSISTION DETECT TIMING ARCHITECTURE FOR A SIMULTANEOUS OPERATION FLASH MEMORY
27
Patent #:
6185128
Issue Dt:
02/06/2001
Application #:
09421984
Filing Dt:
10/19/1999
Title:
REFERENCE CELL FOUR-WAY SWITCH FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
28
Patent #:
6359808
Issue Dt:
03/19/2002
Application #:
09421985
Filing Dt:
10/19/1999
Title:
LOW VOLTAGE READ CASCODE FOR 2V/3V AND DIFFERENT BANK COMBINATIONS WITHOUT METAL OPTIONS FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
29
Patent #:
6259633
Issue Dt:
07/10/2001
Application #:
09422198
Filing Dt:
10/19/1999
Title:
SENSE AMPLIFIER ARCHITECTURE FOR SLIDING BANKS FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
30
Patent #:
6118698
Issue Dt:
09/12/2000
Application #:
09422199
Filing Dt:
10/19/1999
Title:
OUTPUT MULTIPLEXING IMPLEMENTATION FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
31
Patent #:
6248635
Issue Dt:
06/19/2001
Application #:
09426205
Filing Dt:
10/25/1999
Title:
PROCESS FOR FABRICATING A BIT-LINE IN A MONOS DEVICE USING A DUAL LAYER HARD MASK
32
Patent #:
6218227
Issue Dt:
04/17/2001
Application #:
09426239
Filing Dt:
10/25/1999
Title:
METHOD TO GENERATE A MONOS TYPE FLASH CELL USING POLYCRYSTALLINE SILICON AS AN ONO TOP LAYER
33
Patent #:
6248628
Issue Dt:
06/19/2001
Application #:
09426430
Filing Dt:
10/25/1999
Title:
METHOD OF FABRICATING AN ONO DIELECTRIC BY NITRIDATION FOR MNOS MEMORY CELLS
34
Patent #:
6265268
Issue Dt:
07/24/2001
Application #:
09426672
Filing Dt:
10/25/1999
Title:
HIGH TEMPERATURE OXIDE DEPOSITION PROCESS FOR FABRICATING AN ONO FLOATING-GATE ELECTRODE IN A TWO BIT EEPROM DEVICE
35
Patent #:
6117730
Issue Dt:
09/12/2000
Application #:
09427402
Filing Dt:
10/25/1999
Title:
INTEGRATED METHOD BY USING HIGH TEMPERATURE OXIDE FOR TOP OXIDE AND PERIPHERY GATE OXIDE
36
Patent #:
6242305
Issue Dt:
06/05/2001
Application #:
09427404
Filing Dt:
10/25/1999
Title:
PROCESS FOR FABRICATING A BIT-LINE USING BURIED DIFFUSION ISOLATION
37
Patent #:
6448609
Issue Dt:
09/10/2002
Application #:
09429244
Filing Dt:
10/28/1999
Title:
METHOD AND SYSTEM FOR PROVIDINNG A POLYSILICON STRINGER MONITOR
38
Patent #:
6163481
Issue Dt:
12/19/2000
Application #:
09431296
Filing Dt:
10/29/1999
Title:
FLASH MEMORY WORDLINE TRACKING ACROSS WHOLE CHIP
39
Patent #:
6212108
Issue Dt:
04/03/2001
Application #:
09490340
Filing Dt:
01/24/2000
Title:
Distributed voltage charge circuits to reduce sensing time in a memory device
40
Patent #:
6329687
Issue Dt:
12/11/2001
Application #:
09492353
Filing Dt:
01/27/2000
Title:
Two bit flash cell with two floating gate regions
41
Patent #:
6243316
Issue Dt:
06/05/2001
Application #:
09501159
Filing Dt:
02/09/2000
Title:
Voltage boost reset circuit for a flash memory
42
Patent #:
6240040
Issue Dt:
05/29/2001
Application #:
09526239
Filing Dt:
03/15/2000
Title:
Multiple bank simultaneous operation for a flash memory
43
Patent #:
6479411
Issue Dt:
11/12/2002
Application #:
09532347
Filing Dt:
03/21/2000
Title:
METHOD FOR FORMING HIGH QUALITY MULTIPLE THICKNESS OXIDE USING HIGH TEMPERATURE DESCUM
44
Patent #:
6432618
Issue Dt:
08/13/2002
Application #:
09535255
Filing Dt:
03/23/2000
Title:
METHOD FOR FORMING HIGH QUALITY MULTIPLE THICKNESS OXIDE LAYERS BY REDUCING DESCUM INDUCED DEFECTS
45
Patent #:
6461973
Issue Dt:
10/08/2002
Application #:
09535256
Filing Dt:
03/23/2000
Publication #:
US20020058421
Pub Dt:
05/16/2002
Title:
METHOD FOR FORMING HIGH QUALITY MULTIPLE THICKNESS OXIDE LAYERS BY REDUCING DESCUM INDUCED DEFECTS
46
Patent #:
6208556
Issue Dt:
03/27/2001
Application #:
09547556
Filing Dt:
04/12/2000
Title:
Address transition detect timing architecture for a simultaneous operation flash memory device
47
Patent #:
6201737
Issue Dt:
03/13/2001
Application #:
09558764
Filing Dt:
04/26/2000
Title:
Apparatus and method to characterize the threshold distribution in an nrom virtual ground array
48
Patent #:
6208561
Issue Dt:
03/27/2001
Application #:
09593303
Filing Dt:
06/13/2000
Title:
Method to reduce capactive loading in flash memory x-decoder for accurate voltage control at wordlines and select lines
49
Patent #:
6351420
Issue Dt:
02/26/2002
Application #:
09595519
Filing Dt:
06/16/2000
Title:
Voltage boost level clamping circuit for a flash memory
50
Patent #:
6397313
Issue Dt:
05/28/2002
Application #:
09632390
Filing Dt:
08/04/2000
Title:
REDUNDANT DUAL BANK ARCHITECTURE FOR A SIMULTANEOUS OPERATION FLASH MEMORY
51
Patent #:
6229735
Issue Dt:
05/08/2001
Application #:
09638055
Filing Dt:
08/11/2000
Title:
Burst read mode word line boosting
52
Patent #:
6327194
Issue Dt:
12/04/2001
Application #:
09644358
Filing Dt:
08/23/2000
Title:
Precise reference wordline loading compensation for a high density flash memory device
53
Patent #:
6395654
Issue Dt:
05/28/2002
Application #:
09648077
Filing Dt:
08/25/2000
Title:
METHOD OF FORMING ONO FLASH MEMORY DEVICES USING RAPID THERMAL OXIDATION
54
Patent #:
6362051
Issue Dt:
03/26/2002
Application #:
09648361
Filing Dt:
08/25/2000
Title:
METHOD OF FORMING ONO FLASH MEMORY DEVICES USING LOW ENERGY NITROGEN IMPLANTATION
55
Patent #:
6346467
Issue Dt:
02/12/2002
Application #:
09649027
Filing Dt:
08/28/2000
Title:
METHOD OF MAKING TUNGSTEN GATE MOS TRANSISTOR AND MEMORY CELL BY ENCAPSULATING
56
Patent #:
6417082
Issue Dt:
07/09/2002
Application #:
09651684
Filing Dt:
08/30/2000
Title:
Semiconductor structure
57
Patent #:
6429108
Issue Dt:
08/06/2002
Application #:
09652136
Filing Dt:
08/31/2000
Title:
NON-VOLATILE MEMORY DEVICE WITH ENCAPSULATED TUNGSTEN GATE AND METHOD OF MAKING SAME
58
Patent #:
6298007
Issue Dt:
10/02/2001
Application #:
09652742
Filing Dt:
08/31/2000
Title:
Method and apparatus for eliminating false data in a page mode memory device
59
Patent #:
6266284
Issue Dt:
07/24/2001
Application #:
09661356
Filing Dt:
09/14/2000
Title:
Output buffer for external voltage
60
Patent #:
6275421
Issue Dt:
08/14/2001
Application #:
09661358
Filing Dt:
09/14/2000
Title:
Chip enable input buffer
61
Patent #:
6353566
Issue Dt:
03/05/2002
Application #:
09663552
Filing Dt:
09/18/2000
Title:
System and method for tracking sensing speed by an equalization pulse for a high density flash memory device
62
Patent #:
6463516
Issue Dt:
10/08/2002
Application #:
09663765
Filing Dt:
09/18/2000
Title:
VARIABLE SECTOR SIZE FOR A HIGH DENSITY FLASH MEMORY DEVICE
63
Patent #:
6285627
Issue Dt:
09/04/2001
Application #:
09663909
Filing Dt:
09/18/2000
Title:
Address transition detector architecture for a high density flash memory device
64
Patent #:
6324108
Issue Dt:
11/27/2001
Application #:
09667891
Filing Dt:
09/22/2000
Title:
Application of external voltage during array VT testing
65
Patent #:
6438041
Issue Dt:
08/20/2002
Application #:
09668100
Filing Dt:
09/22/2000
Title:
NEGATIVE VOLTAGE REGULATION
66
Patent #:
6400633
Issue Dt:
06/04/2002
Application #:
09675372
Filing Dt:
09/29/2000
Title:
POWER-SAVING MODES FOR MEMORIES
67
Patent #:
6813735
Issue Dt:
11/02/2004
Application #:
09676623
Filing Dt:
10/02/2000
Title:
I/O BASED COLUMN REDUNDANCY FOR VIRTUAL GROUND WITH 2-BIT CELL FLASH MEMORY
68
Patent #:
6310805
Issue Dt:
10/30/2001
Application #:
09676902
Filing Dt:
10/02/2000
Title:
Architecture for a dual-bank page mode memory with redundancy
69
Patent #:
6400638
Issue Dt:
06/04/2002
Application #:
09680344
Filing Dt:
10/05/2000
Title:
Wordline driver for flash memory read mode
70
Patent #:
6583479
Issue Dt:
06/24/2003
Application #:
09688936
Filing Dt:
10/16/2000
Title:
SIDEWALL NROM AND METHOD OF MANUFACTURE THEREOF FOR NON-VOLATILE MEMORY CELLS
71
Patent #:
6373742
Issue Dt:
04/16/2002
Application #:
09689036
Filing Dt:
10/12/2000
Title:
Two side decoding of a memory array
72
Patent #:
6347052
Issue Dt:
02/12/2002
Application #:
09690554
Filing Dt:
10/17/2000
Title:
Word line decoding architecture in a flash memory
73
Patent #:
6537866
Issue Dt:
03/25/2003
Application #:
09691643
Filing Dt:
10/18/2000
Title:
METHOD OF FORMING NARROW INSULATING SPACERS FOR USE IN REDUCING MINIMUM COMPONENT SIZE
74
Patent #:
6507527
Issue Dt:
01/14/2003
Application #:
09698614
Filing Dt:
10/27/2000
Title:
MEMORY LINE DISCHARGE BEFORE SENSING
75
Patent #:
6297993
Issue Dt:
10/02/2001
Application #:
09712382
Filing Dt:
11/13/2000
Title:
Acceleration voltage implementation for a high density flash memory device
76
Patent #:
6465306
Issue Dt:
10/15/2002
Application #:
09723635
Filing Dt:
11/28/2000
Title:
SIMULTANEOUS FORMATION OF CHARGE STORAGE AND BITLINE TO WORDLINE ISOLATION
77
Patent #:
6468865
Issue Dt:
10/22/2002
Application #:
09723653
Filing Dt:
11/28/2000
Title:
METHOD OF SIMULTANEOUS FORMATION OF BITLINE ISOLATION AND PERIPHEY OXIDE
78
Patent #:
6622230
Issue Dt:
09/16/2003
Application #:
09724675
Filing Dt:
11/28/2000
Title:
MULTI-SET BLOCK ERASE
79
Patent #:
6463003
Issue Dt:
10/08/2002
Application #:
09729388
Filing Dt:
12/04/2000
Publication #:
US20010050874
Pub Dt:
12/13/2001
Title:
POWER SAVING SCHEME FOR BURST MODE IMPLEMENTATION DURING READING OF DATA FROM A MEMORY DEVICE
80
Patent #:
6445030
Issue Dt:
09/03/2002
Application #:
09772600
Filing Dt:
01/30/2001
Title:
FLASH MEMORY ERASE SPEED BY FLUORINE IMPLANT OR FLUORINATION
81
Patent #:
6528390
Issue Dt:
03/04/2003
Application #:
09798667
Filing Dt:
03/02/2001
Publication #:
US20020132446
Pub Dt:
09/19/2002
Title:
PROCESS FOR FABRICATING A NON-VOLATILE MEMORY DEVICE
82
Patent #:
6713809
Issue Dt:
03/30/2004
Application #:
09809969
Filing Dt:
03/16/2001
Title:
DUAL BIT MEMORY DEVICE WITH ISOLATED POLYSILICON FLOATING GATES
83
Patent #:
6573140
Issue Dt:
06/03/2003
Application #:
09810155
Filing Dt:
03/16/2001
Title:
PROCESS FOR MAKING A DUAL BIT MEMORY DEVICE WITH ISOLATED POLYSILICON FLOATING GATES
84
Patent #:
6385093
Issue Dt:
05/07/2002
Application #:
09822995
Filing Dt:
03/30/2001
Title:
I/O partitioning system and methodology to reduce band-to-band tunneling current during erase
85
Patent #:
6493266
Issue Dt:
12/10/2002
Application #:
09829193
Filing Dt:
04/09/2001
Publication #:
US20030021155
Pub Dt:
01/30/2003
Title:
SOFT PROGRAM AND SOFT PROGRAM VERIFY OF THE CORE CELLS IN FLASH MEMORY ARRAY
86
Patent #:
6621761
Issue Dt:
09/16/2003
Application #:
09829518
Filing Dt:
04/09/2001
Publication #:
US20020012278
Pub Dt:
01/31/2002
Title:
BURST ARCHITECTURE FOR A FLASH MEMORY
87
Patent #:
6381163
Issue Dt:
04/30/2002
Application #:
09873927
Filing Dt:
06/04/2001
Title:
METHODS AND APPARATUS FOR READING A CAM CELL USING BOOSTED AND REGULATED GATE VOLTAGE
88
Patent #:
6370061
Issue Dt:
04/09/2002
Application #:
09884583
Filing Dt:
06/19/2001
Title:
Ceiling test mode to characterize the threshold voltage distribution of over programmed memory cells
89
Patent #:
6633949
Issue Dt:
10/14/2003
Application #:
09892431
Filing Dt:
06/26/2001
Publication #:
US20020010828
Pub Dt:
01/24/2002
Title:
BANK SELECTOR CIRCUIT FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE WITH A FLEXIBLE BANK PARTITION ARCHITECTURE
90
Patent #:
6436768
Issue Dt:
08/20/2002
Application #:
09893279
Filing Dt:
06/27/2001
Title:
SOURCE DRAIN IMPLANT DURING ONO FORMATION FOR IMPROVED ISOLATION OF SONOS DEVICES
91
Patent #:
6535424
Issue Dt:
03/18/2003
Application #:
09915018
Filing Dt:
07/25/2001
Publication #:
US20030021152
Pub Dt:
01/30/2003
Title:
VOLTAGE BOOST CIRCUIT USING SUPPLY VOLTAGE DETECTION TO COMPENSATE FOR SUPPLY VOLTAGE VARIATIONS IN READ MODE VOLTAGES
92
Patent #:
6525969
Issue Dt:
02/25/2003
Application #:
09928059
Filing Dt:
08/10/2001
Title:
DECODER APPARATUS AND METHODS FOR PRE-CHARGING BIT LINES
93
Patent #:
6566736
Issue Dt:
05/20/2003
Application #:
09998624
Filing Dt:
11/30/2001
Title:
DIE SEAL FOR SEMICONDUCTOR DEVICE MOISTURE PROTECTION
94
Patent #:
6510082
Issue Dt:
01/21/2003
Application #:
09999869
Filing Dt:
10/23/2001
Title:
DRAIN SIDE SENSING SCHEME FOR VIRTUAL GROUND FLASH EPROM ARRAY WITH ADJACENT BIT CHARGE AND HOLD
95
Patent #:
6828199
Issue Dt:
12/07/2004
Application #:
10022798
Filing Dt:
12/20/2001
Publication #:
US20030119314
Pub Dt:
06/26/2003
Title:
MONOS DEVICE HAVING BURIED METAL SILICIDE BIT LINE
96
Patent #:
6809033
Issue Dt:
10/26/2004
Application #:
10045354
Filing Dt:
11/07/2001
Title:
INNOVATIVE METHOD OF HARD MASK REMOVAL
97
Patent #:
6611473
Issue Dt:
08/26/2003
Application #:
10061620
Filing Dt:
02/01/2002
Publication #:
US20020071331
Pub Dt:
06/13/2002
Title:
POWER-SAVING MODES FOR MEMORIES
98
Patent #:
6750103
Issue Dt:
06/15/2004
Application #:
10086112
Filing Dt:
02/27/2002
Title:
NROM CELL WITH N-LESS CHANNEL
99
Patent #:
6706595
Issue Dt:
03/16/2004
Application #:
10100485
Filing Dt:
03/14/2002
Publication #:
US20040014290
Pub Dt:
01/22/2004
Title:
HARD MASK PROCESS FOR MEMORY DEVICE WITHOUT BITLINE SHORTS
100
Patent #:
6803265
Issue Dt:
10/12/2004
Application #:
10109234
Filing Dt:
03/27/2002
Title:
LINER FOR SEMICONDUCTOR MEMORIES AND MANUFACTURING METHOD THEREFOR
Assignor
1
FASL LLC
Exec Dt:
04/01/2010
Assignee
1
SPANSION LLC
915 DEGUIGNE DRIVE
M/S 250
SUNNYVALE, CALIFORNIA 94088
Correspondence name and address
PETER Y. WANG
915 DEGUIGNE DRIVE
M/S 250
SUNNYVALE, CA 94088

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