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Total properties:
20
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Patent #:
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Issue Dt:
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10/24/1995
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Application #:
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08373006
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Filing Dt:
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01/17/1995
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Title:
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MANUFACTURING METHOD FOR A SELF-ALIGNED THROUGH HOLE AND SEMICONDUCTOR STRUCTURE
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Patent #:
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Issue Dt:
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07/14/1998
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Application #:
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08744132
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Filing Dt:
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11/05/1996
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Title:
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FORMATION OF SILICIDED JUNCTIONS IN DEEP SUBMICRON MOSFETS BY DEFECT ENHANCED COS12 FORMATION
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Patent #:
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Issue Dt:
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08/25/1998
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Application #:
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08841030
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Filing Dt:
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04/29/1997
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Title:
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METHOD OF MANUFACTURING METAL INTERCONNECT STRUCTURE FOR AN INTEGRATED CIRCUIT WITH IMPROVED ELECTROMIGRATION RELIABILITY
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Patent #:
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Issue Dt:
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08/03/1999
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Application #:
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08929590
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Filing Dt:
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09/15/1997
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Title:
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METHOD TO MINIMIZE WATERMARKS ON SILICON SUBSTRATES
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Patent #:
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Issue Dt:
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02/15/2000
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Application #:
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09061538
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Filing Dt:
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04/16/1998
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Title:
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CRACK STOPS
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Patent #:
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Issue Dt:
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01/23/2001
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Application #:
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09153390
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Filing Dt:
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09/15/1998
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Title:
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METALLIZATION ETCHING TECHNIQUES FOR REDUCING POST-ETCH CORROSION OF METAL LINES
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Patent #:
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Issue Dt:
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09/07/2004
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Application #:
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09210912
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Filing Dt:
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12/14/1998
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Title:
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METHOD OF CONTROLLED CHEMICAL VAPOR DEPOSITION OF A METAL OXIDE CERAMIC LAYER
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Patent #:
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Issue Dt:
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08/07/2001
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Application #:
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09218882
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Filing Dt:
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12/22/1998
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Title:
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CRACK STOPS
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Patent #:
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Issue Dt:
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07/04/2000
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Application #:
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09241741
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Filing Dt:
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12/22/1998
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Title:
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CRACK STOPS
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Patent #:
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Issue Dt:
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02/05/2002
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Application #:
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09523862
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Filing Dt:
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03/14/2000
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Title:
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DUMMY PATTERNS FOR ALUMINUM CHEMICAL POLISHING (CMP)
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Patent #:
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Issue Dt:
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10/28/2003
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Application #:
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09524240
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Filing Dt:
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03/13/2000
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Title:
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CIRCUIT CONFIGURATION FOR THE INTERFERENCE- FREE INITIALIZATION OF DELAYED LOCKED LOOP CIRCUITS WITH FAST LOCK
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Patent #:
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Issue Dt:
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11/19/2002
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Application #:
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09562217
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Filing Dt:
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04/28/2000
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Title:
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SEMICONDUCTOR DEVICE STRUCTURE WITH HYDROGEN-RICH LAYER FOR FACILITATING PASSIVATION OF SURFACE STATES
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Patent #:
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Issue Dt:
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09/02/2003
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Application #:
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09636521
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Filing Dt:
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08/10/2000
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Title:
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OPTICAL STRUCTURE AND METHOD FOR PRODUCING THE SAME
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Patent #:
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Issue Dt:
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12/04/2007
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Application #:
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09680923
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Filing Dt:
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10/06/2000
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Title:
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SYSTEM AND METHOD FOR MANAGING RISK AND OPPORTUNITY
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Patent #:
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Issue Dt:
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12/24/2002
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Application #:
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09730674
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Filing Dt:
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12/06/2000
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Publication #:
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Pub Dt:
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06/06/2002
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Title:
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NEGATIVE ION IMPLANT MASK FORMATION FOR SELF-ALIGNED, SUBLITHOGRAPHIC RESOLUTION PATTERNING FOR SINGLE-SIDED VERTICAL DEVICE FORMATION
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Patent #:
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Issue Dt:
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09/30/2003
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Application #:
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09767806
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Filing Dt:
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01/22/2001
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Publication #:
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Pub Dt:
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11/08/2001
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Title:
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RESISTIVE FERROELECTRIC MEMORY CELL
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Patent #:
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Issue Dt:
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05/04/2004
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Application #:
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09873138
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Filing Dt:
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06/01/2001
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Publication #:
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Pub Dt:
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11/15/2001
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Title:
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LOW TEMPERATURE CHEMICAL VAPOR DEPOSITION PROCESS FOR FORMING BISMUTH-CONTAINING CERAMIC THIN FILMS USEFUL IN FERROELECTRIC MEMORY DEVICES
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Patent #:
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Issue Dt:
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04/15/2003
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Application #:
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09987956
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Filing Dt:
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11/16/2001
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Title:
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SPACER FORMATION PROCESS USING OXIDE SHIELD
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Patent #:
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Issue Dt:
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07/27/2004
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Application #:
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10438352
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Filing Dt:
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05/14/2003
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Publication #:
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Pub Dt:
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01/01/2004
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Title:
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CIRCUIT WITH BURIED STRAP INCLUDING LINER
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Patent #:
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Issue Dt:
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01/01/2008
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Application #:
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11636616
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Filing Dt:
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12/11/2006
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Publication #:
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Pub Dt:
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04/12/2007
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Title:
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HYBRID MEMORY CELL FOR SPIN-POLARIZED ELECTRON CURRENT INDUCED SWITCHING AND WRITING/READING PROCESS USING SUCH MEMORY CELL
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