|
Total properties:
11
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/16/2011
|
Application #:
|
12008841
|
Filing Dt:
|
01/15/2008
|
|
Publication #:
|
|
Pub Dt:
|
07/16/2009
| | | | |
|
Title:
|
STRAIN-DIRECT-ON-INSULATOR (SDOI) SUBSTRATE AND METHOD OF FORMING
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12009204
|
Filing Dt:
|
01/17/2008
|
|
Publication #:
|
|
Pub Dt:
|
07/23/2009
| | | | |
|
Title:
|
Elimination of STI recess and facet growth in embedded silicon-germanium (eSiGe) module
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12154605
|
Filing Dt:
|
05/23/2008
|
|
Publication #:
|
|
Pub Dt:
|
11/26/2009
| | | | |
|
Title:
|
High shrinkage stress silicon nitride (SiN) layer for NFET improvement
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12214854
|
Filing Dt:
|
06/23/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/24/2009
| | | | |
|
Title:
|
Implantation for shallow trench isolation (STI) formation and for stress for transistor performance enhancement
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/23/2012
|
Application #:
|
12220792
|
Filing Dt:
|
07/28/2008
|
|
Publication #:
|
|
Pub Dt:
|
01/28/2010
| | | | |
|
Title:
|
METHOD AND APPARATUS TO REDUCE THERMAL VARIATIONS WITHIN AN INTEGRATED CIRCUIT DIE USING THERMAL PROXIMITY CORRECTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/01/2011
|
Application #:
|
12378513
|
Filing Dt:
|
02/17/2009
|
|
Publication #:
|
|
Pub Dt:
|
08/19/2010
| | | | |
|
Title:
|
FABRICATING METHOD FOR CRACK STOP STRUCTURE ENHANCEMENT OF INTEGRATED CIRCUIT SEAL RING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/10/2014
|
Application #:
|
12456440
|
Filing Dt:
|
06/16/2009
|
|
Publication #:
|
|
Pub Dt:
|
12/16/2010
| | | | |
|
Title:
|
NON-VOLATILE MEMORY UTILIZING IMPACT IONIZATION AND TUNNELLING AND METHOD OF MANUFACTURING THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/21/2013
|
Application #:
|
12583486
|
Filing Dt:
|
08/21/2009
|
|
Publication #:
|
|
Pub Dt:
|
02/24/2011
| | | | |
|
Title:
|
Non-volatile memory using pyramidal nanocrystals as electron storage elements
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12584137
|
Filing Dt:
|
09/01/2009
|
|
Publication #:
|
|
Pub Dt:
|
03/03/2011
| | | | |
|
Title:
|
Method for forming an ultrathin Cu barrier/seed bilayer for integrated circuit device fabrication
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/05/2013
|
Application #:
|
12587511
|
Filing Dt:
|
10/08/2009
|
|
Publication #:
|
|
Pub Dt:
|
04/14/2011
| | | | |
|
Title:
|
METHOD OF FABRICATING A SILICON TUNNELING FIELD EFFECT TRANSISTOR (TFET) WITH HIGH DRIVE CURRENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/25/2014
|
Application #:
|
12649212
|
Filing Dt:
|
12/29/2009
|
|
Publication #:
|
|
Pub Dt:
|
06/30/2011
| | | | |
|
Title:
|
LIQUID IMMERSION SCANNING EXPOSURE SYSTEM USING AN IMMERSION LIQUID CONFINED WITHIN A LENS HOOD
|
|
