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Patent #:
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|
Issue Dt:
|
10/10/2006
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Application #:
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10841850
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Filing Dt:
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05/07/2004
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Title:
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FLASH MEMORY CELL AND METHODS FOR PROGRAMMING AND ERASING
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Patent #:
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Issue Dt:
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12/13/2005
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Application #:
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10841933
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Filing Dt:
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05/06/2004
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Title:
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STRUCTURE AND METHOD FOR PROTECTING MEMORY CELLS FROM UV RADIATION DAMAGE AND UV RADIATION-INDUCED CHARGING DURING BACKEND PROCESSING
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Patent #:
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Issue Dt:
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01/24/2006
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Application #:
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10843289
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Filing Dt:
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05/11/2004
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Publication #:
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Pub Dt:
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11/17/2005
| | | | |
Title:
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BITLINE IMPLANT UTILIZING DUAL POLY
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Patent #:
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Issue Dt:
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04/26/2005
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Application #:
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10844116
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Filing Dt:
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05/12/2004
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Title:
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CASCODE AMPLIFIER CIRCUIT FOR GENERATING AND MAINTAINING A FAST, STABLE AND ACCURATE BIT LINE VOLTAGE
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Patent #:
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Issue Dt:
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12/27/2005
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Application #:
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10848679
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Filing Dt:
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05/19/2004
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Publication #:
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Pub Dt:
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11/04/2004
| | | | |
Title:
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STACKED ORGANIC MEMORY DEVICES AND METHODS OF OPERATING AND FABRICATING
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Patent #:
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Issue Dt:
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12/19/2006
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Application #:
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10859369
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Filing Dt:
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06/01/2004
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Title:
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METHOD AND DEVICE FOR REDUCING INTERFACE AREA OF A MEMORY DEVICE
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Patent #:
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Issue Dt:
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03/07/2006
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Application #:
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10860450
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Filing Dt:
|
06/03/2004
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Title:
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METHOD OF DETERMINING VOLTAGE COMPENSATION FOR FLASH MEMORY DEVICES
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Patent #:
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Issue Dt:
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08/15/2006
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Application #:
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10861437
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Filing Dt:
|
06/03/2004
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Title:
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UV-BLOCKING ETCH STOP LAYER FOR REDUCING UV-INDUCED CHARGING OF CHARGE STORAGE LAYER IN MEMORY DEVICES IN BEOL PROCESSING
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Patent #:
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Issue Dt:
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06/05/2007
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Application #:
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10861575
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Filing Dt:
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06/04/2004
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Title:
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METHOD AND SYSTEM FOR IMPROVING THE TOPOGRAPHY OF A MEMORY ARRAY
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Patent #:
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Issue Dt:
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02/13/2007
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Application #:
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10862636
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Filing Dt:
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06/07/2004
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Title:
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LDC IMPLANT FOR MIRRORBIT TO IMPROVE VT ROLL-OFF AND FORM SHARPER JUNCTION
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Patent #:
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Issue Dt:
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12/21/2004
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Application #:
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10863673
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Filing Dt:
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06/08/2004
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Title:
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MEMORY DEVICE AND METHODS OF USING NEGATIVE GATE STRESS TO CORRECT OVER-ERASED MEMORY CELLS
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Patent #:
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Issue Dt:
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08/23/2005
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Application #:
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10863933
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Filing Dt:
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06/09/2004
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Title:
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RAMP SOURCE HOT-HOLE PROGRAMMING FOR TRAP BASED NON-VOLATILE MEMORY DEVICES
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Patent #:
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Issue Dt:
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05/30/2006
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Application #:
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10864142
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Filing Dt:
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06/08/2004
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Title:
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MEMORY WORDLINE SPACER
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Patent #:
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Issue Dt:
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07/31/2007
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Application #:
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10864947
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Filing Dt:
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06/10/2004
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Publication #:
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Pub Dt:
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12/15/2005
| | | | |
Title:
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ERASE ALGORITHM FOR MULTI-LEVEL BIT FLASH MEMORY
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Patent #:
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Issue Dt:
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08/29/2006
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Application #:
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10869286
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Filing Dt:
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06/16/2004
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Title:
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ALIGNMENT MARKS WITH SALICIDED SPACERS BETWEEN BITLINES FOR ALIGNMENT SIGNAL IMPROVEMENT
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Patent #:
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Issue Dt:
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02/07/2006
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Application #:
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10869774
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Filing Dt:
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06/16/2004
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Title:
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SEMICONDUCTOR DEVICE WITH CORE AND PERIPHERY REGIONS
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Patent #:
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Issue Dt:
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12/05/2006
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Application #:
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10873069
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Filing Dt:
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06/21/2004
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Title:
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ELECTRICALLY ADDRESSABLE MEMORY SWITCH
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Patent #:
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Issue Dt:
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02/07/2006
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Application #:
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10878091
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Filing Dt:
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06/28/2004
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Publication #:
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Pub Dt:
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11/25/2004
| | | | |
Title:
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MEMORY DEVICE HAVING A P+ GATE AND THIN BOTTOM OXIDE AND METHOD OF ERASING SAME
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Patent #:
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Issue Dt:
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09/13/2005
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Application #:
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10882538
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Filing Dt:
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06/30/2004
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Publication #:
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Pub Dt:
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12/09/2004
| | | | |
Title:
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CONTROL OF MEMORY ARRAYS UTILIZING ZENER DIODE-LIKE DEVICES
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Patent #:
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Issue Dt:
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01/02/2007
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Application #:
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10883350
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Filing Dt:
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07/01/2004
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Publication #:
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Pub Dt:
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01/05/2006
| | | | |
Title:
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SWITCHABLE MEMORY DIODE - A NEW MEMORY DEVICE
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Patent #:
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Issue Dt:
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01/10/2006
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Application #:
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10883924
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Filing Dt:
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07/01/2004
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Title:
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FLOATING GATE SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE
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Patent #:
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Issue Dt:
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01/17/2006
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Application #:
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10885268
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Filing Dt:
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07/06/2004
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Publication #:
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Pub Dt:
|
01/12/2006
| | | | |
Title:
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METHOD OF IMPROVING ERASE VOLTAGE DISTRIBUTION FOR A FLASH MEMORY ARRAY HAVING DUMMY WORDLINES
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Patent #:
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Issue Dt:
|
07/04/2006
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Application #:
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10885284
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Filing Dt:
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07/06/2004
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Title:
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ARCHITECTURE FOR GENERATING ADAPTIVE ARBITRARY WAVEFORMS
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Patent #:
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Issue Dt:
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05/17/2005
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Application #:
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10885944
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Filing Dt:
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07/07/2004
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Title:
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CUS FORMATION BY ANODIC SULFIDE PASSIVATION OF COPPER SURFACE
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Patent #:
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Issue Dt:
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07/10/2007
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Application #:
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10887585
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Filing Dt:
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07/08/2004
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Publication #:
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Pub Dt:
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01/12/2006
| | | | |
Title:
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BOND PAD STRUCTURE FOR COPPER METALLIZATION HAVING INCREASED RELIABILITY AND METHOD FOR FABRICATING SAME
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Patent #:
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Issue Dt:
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03/28/2006
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Application #:
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10887782
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Filing Dt:
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07/09/2004
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Title:
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METHOD OF REFERENCE CELL DESIGN FOR OPTIMIZED MEMORY CIRCUIT YIELD
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Patent #:
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Issue Dt:
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11/29/2005
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Application #:
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10889424
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Filing Dt:
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07/12/2004
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Title:
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ONO FABRICATION PROCESS FOR REDUCING OXYGEN VACANCY CONTENT IN BOTTOM OXIDE LAYER IN FLASH MEMORY DEVICES
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Patent #:
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Issue Dt:
|
09/09/2008
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Application #:
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10896292
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Filing Dt:
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07/20/2004
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Title:
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APPARATUS AND METHOD FOR A MEMORY ARRAY WITH SHALLOW TRENCH ISOLATION REGIONS BETWEEN BIT LINES FOR INCREASED PROCESS MARGINS
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Patent #:
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Issue Dt:
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07/18/2006
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Application #:
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10896299
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Filing Dt:
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07/20/2004
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Title:
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METHOD FOR PROGRAMMING DUAL BIT MEMORY DEVICES TO REDUCE COMPLEMENTARY BIT DISTURBANCE
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Patent #:
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Issue Dt:
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05/09/2006
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Application #:
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10896651
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Filing Dt:
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07/22/2004
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Title:
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METHOD OF PROGRAMMING A FLASH MEMORY DEVICE USING MULTILEVEL CHARGE STORAGE
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Patent #:
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Issue Dt:
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12/11/2007
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Application #:
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10899344
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Filing Dt:
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07/26/2004
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Title:
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THREE DIMENSIONAL POLYMER MEMORY CELL SYSTEMS
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Patent #:
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Issue Dt:
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08/15/2006
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Application #:
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10899684
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Filing Dt:
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07/26/2004
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Title:
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METHOD FOR PULSE ERASE IN DUAL BIT MEMORY DEVICES
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Patent #:
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Issue Dt:
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01/02/2007
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Application #:
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10899873
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Filing Dt:
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07/27/2004
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Publication #:
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Pub Dt:
|
06/02/2005
| | | | |
Title:
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MOLECULAR MEMORY DEVICE
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Patent #:
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Issue Dt:
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06/20/2006
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Application #:
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10900832
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Filing Dt:
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07/28/2004
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Title:
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METHODS OF DETERMINING CHARACTERISTICS OF DOPED REGIONS ON DEVICE WAFERS, AND SYSTEM FOR ACCOMPLISHING SAME
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Patent #:
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Issue Dt:
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05/09/2006
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Application #:
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10909693
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Filing Dt:
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08/02/2004
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Publication #:
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Pub Dt:
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02/02/2006
| | | | |
Title:
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FLASH MEMORY UNIT AND METHOD OF PROGRAMMING A FLASH MEMORY DEVICE
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Patent #:
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Issue Dt:
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01/30/2007
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Application #:
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10915771
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Filing Dt:
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08/11/2004
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Publication #:
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Pub Dt:
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02/16/2006
| | | | |
Title:
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MEMORY CELL WITH REDUCED DIBL AND VSS RESISTANCE
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Patent #:
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Issue Dt:
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03/24/2009
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Application #:
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10916167
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Filing Dt:
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08/11/2004
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Publication #:
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Pub Dt:
|
02/16/2006
| | | | |
Title:
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METHOD OF FORMING NARROWLY SPACED FLASH MEMORY CONTACT OPENINGS AND LITHOGRAPHY MASKS
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Patent #:
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Issue Dt:
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01/02/2007
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Application #:
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10917562
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Filing Dt:
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08/13/2004
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Title:
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USING THIN UNDOPED TEOS WITH BPTEOS ILD OR BPTEOS ILD ALONE TO IMPROVE CHARGE LOSS AND CONTACT RESISTANCE IN MULTI BIT MEMORY DEVICES
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Patent #:
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Issue Dt:
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12/20/2005
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Application #:
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10919119
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Filing Dt:
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08/16/2004
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Title:
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TEST STRUCTURE FOR CHARACTERIZING JUNCTION LEAKAGE CURRENT
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Patent #:
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Issue Dt:
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04/03/2007
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Application #:
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10919572
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Filing Dt:
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08/17/2004
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Publication #:
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Pub Dt:
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02/23/2006
| | | | |
Title:
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POLYMER MEMORY DEVICE WITH VARIABLE PERIOD OF RETENTION TIME
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Patent #:
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Issue Dt:
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10/30/2007
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Application #:
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10919846
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Filing Dt:
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08/17/2004
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Publication #:
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Pub Dt:
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02/23/2006
| | | | |
Title:
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SYSTEMS AND METHODS FOR ADJUSTING PROGRAMMING THRESHOLDS OF POLYMER MEMORY CELLS
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Patent #:
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Issue Dt:
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10/17/2006
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Application #:
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10919872
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Filing Dt:
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08/17/2004
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Title:
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METHOD TO IMPROVE YIELD AND SIMPLIFY OPERATION OF POLYMER MEMORY CELLS
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10928354
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Filing Dt:
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08/27/2004
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Publication #:
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Pub Dt:
|
03/02/2006
| | | | |
Title:
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Deposition of hard-mask with minimized hillocks and bubbles
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Patent #:
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Issue Dt:
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12/19/2006
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Application #:
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10928582
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Filing Dt:
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08/27/2004
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Title:
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SONOS MEMORY WITH INVERSION BIT-LINES
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Patent #:
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Issue Dt:
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08/05/2008
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Application #:
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10928665
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Filing Dt:
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08/27/2004
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Title:
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SEMICONDUCTOR COMPONENT HAVING A CONTACT STRUCTURE AND METHOD OF MANUFACTURE
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Patent #:
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Issue Dt:
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09/05/2006
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Application #:
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10933588
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Filing Dt:
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09/03/2004
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Title:
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SYSTEM AND METHOD FOR MULTI-BIT FLASH READS USING DUAL DYNAMIC REFERENCES
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Patent #:
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Issue Dt:
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08/11/2009
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Application #:
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10934828
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Filing Dt:
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09/02/2004
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Title:
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SEMICONDUCTOR FORMATION METHOD THAT UTILIZES MULTIPLE ETCH STOP LAYERS
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Patent #:
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Issue Dt:
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04/22/2008
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Application #:
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10934923
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Filing Dt:
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09/02/2004
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Title:
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SEMICONDUCTOR CONTACT AND NITRIDE SPACER FORMATION SYSTEM AND METHOD
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Patent #:
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NONE
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Issue Dt:
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|
Application #:
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10935301
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Filing Dt:
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09/07/2004
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Publication #:
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Pub Dt:
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03/09/2006
| | | | |
Title:
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Vertical JFET as used for selective component in a memory array
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Patent #:
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Issue Dt:
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10/31/2006
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Application #:
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10939773
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Filing Dt:
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09/13/2004
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Title:
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METHOD AND STRUCTURE OF MEMORY ELEMENT PLUG WITH CONDUCTIVE TA REMOVED FROM SIDEWALL AT REGION OF MEMORY ELEMENT FILM
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Patent #:
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Issue Dt:
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11/14/2006
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Application #:
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10939775
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Filing Dt:
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09/13/2004
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Title:
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METHOD OF MAKING A SEMICONDUCTOR STRUCTURE
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Patent #:
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Issue Dt:
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12/12/2006
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Application #:
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10939897
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Filing Dt:
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09/13/2004
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Title:
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METHOD OF FORMING COPPER SULFIDE LAYER OVER SUBSTRATE
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Patent #:
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Issue Dt:
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07/18/2006
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Application #:
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10945914
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Filing Dt:
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09/22/2004
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Title:
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METHODS AND SYSTEMS FOR REDUCING ERASE TIMES IN FLASH MEMORY DEVICES
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Patent #:
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Issue Dt:
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05/02/2006
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Application #:
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10946809
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Filing Dt:
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09/22/2004
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Publication #:
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Pub Dt:
|
03/23/2006
| | | | |
Title:
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READ APPROACH FOR MULTI-LEVEL VIRTUAL GROUND MEMORY
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Patent #:
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Issue Dt:
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08/19/2008
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Application #:
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10946812
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Filing Dt:
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09/22/2004
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Title:
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PAGE_ EXE ERASE ALGORITHM FOR FLASH MEMORY
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Patent #:
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Issue Dt:
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04/12/2005
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Application #:
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10951370
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Filing Dt:
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09/28/2004
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Publication #:
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Pub Dt:
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03/03/2005
| | | | |
Title:
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PHOTOSENSITIVE POLYMERIC MEMORY ELEMENTS
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Patent #:
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Issue Dt:
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06/27/2006
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Application #:
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10951410
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Filing Dt:
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09/28/2004
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Title:
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SYSTEM THAT FACILITATES READING MULTI-LEVEL DATA IN NON-VOLATILE MEMORY
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Patent #:
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Issue Dt:
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10/03/2006
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Application #:
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10957247
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Filing Dt:
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10/01/2004
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Title:
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SO2 TREATMENT OF OXIDIZED CUO FOR COPPER SULFIDE FORMATION OF MEMORY ELEMENT GROWTH
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Patent #:
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Issue Dt:
|
11/13/2007
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Application #:
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10958044
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Filing Dt:
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10/04/2004
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Title:
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MEMORY DEVICE WITH A SELF-ASSEMBLED POLYMER FILM AND METHOD OF MAKING THE SAME
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Patent #:
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Issue Dt:
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04/17/2007
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Application #:
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10968414
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Filing Dt:
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10/19/2004
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Title:
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NON-VOLATILE MEMORY SYSTEM HAVING A PROGRAMMABLY SELECTABLE BOOT CODE SECTION SIZE
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Patent #:
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Issue Dt:
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06/27/2006
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Application #:
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10968705
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Filing Dt:
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10/19/2004
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Title:
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ION PATH POLYMERS FOR ION-MOTION MEMORY
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Patent #:
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Issue Dt:
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03/28/2006
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Application #:
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10968713
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Filing Dt:
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10/19/2004
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Title:
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PATTERNING FOR ELONGATED VSS CONTACT FLASH MEMORY
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|
Patent #:
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NONE
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Issue Dt:
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|
Application #:
|
10975629
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Filing Dt:
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10/28/2004
|
Publication #:
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Pub Dt:
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05/04/2006
| | | | |
Title:
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System and method for improved memory performance in a mobile device
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Patent #:
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Issue Dt:
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10/06/2009
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Application #:
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10976760
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Filing Dt:
|
11/01/2004
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Title:
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FLASH MEMORY DEVICE HAVING INCREASED OVER-ERASE CORRECTION EFFICIENCY AND ROBUSTNESS AGAINST DEVICE VARIATIONS
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Patent #:
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Issue Dt:
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07/22/2008
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Application #:
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10976816
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Filing Dt:
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11/01/2004
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Publication #:
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Pub Dt:
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05/04/2006
| | | | |
Title:
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SYSTEM AND METHOD FOR PROTECTING SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
|
06/26/2007
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Application #:
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10976876
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Filing Dt:
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11/01/2004
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Title:
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SEMICONDUCTOR DEVICE WITH ELECTRICALLY BIASED DIE EDGE SEAL
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Patent #:
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Issue Dt:
|
05/22/2007
|
Application #:
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10978621
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Filing Dt:
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11/01/2004
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Title:
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POLYMER MEMORY CELL OPERATION
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Patent #:
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Issue Dt:
|
05/20/2008
|
Application #:
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10978845
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Filing Dt:
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11/01/2004
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Title:
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METHOD OF MAKING AN ORGANIC MEMORY CELL
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Patent #:
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Issue Dt:
|
11/28/2006
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Application #:
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10979516
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Filing Dt:
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11/02/2004
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Title:
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METHOD OF MAKING A MEMORY CELL
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Patent #:
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Issue Dt:
|
01/15/2008
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Application #:
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10981026
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Filing Dt:
|
11/04/2004
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Title:
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METHOD FOR ISOLATING A FAILURE SITE IN A WORDLINE IN A MEMORY ARRAY
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Patent #:
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Issue Dt:
|
12/19/2006
|
Application #:
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10981174
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Filing Dt:
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11/04/2004
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Title:
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MEMORY CELL WITH PLASMA-GROWN OXIDE SPACER FOR REDUCED DIBL AND VSS RESISTANCE AND INCREASED RELIABILITY
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Patent #:
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Issue Dt:
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03/28/2006
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Application #:
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10981833
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Filing Dt:
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11/04/2004
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Title:
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RAMPED SOFT PROGRAMMING FOR CONTROL OF ERASE VOLTAGE DISTRIBUTIONS IN FLASH MEMORY DEVICES
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Patent #:
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Issue Dt:
|
05/02/2006
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Application #:
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10982296
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Filing Dt:
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11/05/2004
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Title:
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MULTI BIT PROGRAM ALGORITHM
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Patent #:
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Issue Dt:
|
10/28/2008
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Application #:
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10983919
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Filing Dt:
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11/08/2004
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Publication #:
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Pub Dt:
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03/30/2006
| | | | |
Title:
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CONTROL OF MEMORY DEVICES POSSESSING VARIABLE RESISTANCE CHARACTERISTICS
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Patent #:
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Issue Dt:
|
04/03/2007
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Application #:
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10985172
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Filing Dt:
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11/10/2004
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Title:
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SYSTEMS AND METHODS FOR A MEMORY AND/OR SELECTION ELEMENT FORMED WITHIN A RECESS IN A METAL LINE
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Patent #:
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Issue Dt:
|
08/01/2006
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Application #:
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10986652
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Filing Dt:
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11/12/2004
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Publication #:
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Pub Dt:
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04/28/2005
| | | | |
Title:
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SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
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Patent #:
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Issue Dt:
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05/22/2007
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Application #:
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10987262
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Filing Dt:
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11/12/2004
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Publication #:
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Pub Dt:
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05/18/2006
| | | | |
Title:
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PROTECTION OF ACTIVE LAYERS OF MEMORY CELLS DURING PROCESSING OF OTHER ELEMENTS
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Patent #:
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Issue Dt:
|
06/19/2007
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Application #:
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10988239
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Filing Dt:
|
11/12/2004
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Title:
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UTILIZATION OF A TA-CONTAINING CAP OVER COPPER TO FACILITATE CONCURRENT FORMATION OF COPPER VIAS AND MEMORY ELEMENT STRUCTURES
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Patent #:
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Issue Dt:
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04/25/2006
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Application #:
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10990706
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Filing Dt:
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11/17/2004
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Publication #:
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Pub Dt:
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05/18/2006
| | | | |
Title:
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DIODE ARRAY ARCHITECTURE FOR ADDRESSING NANOSCALE RESISTIVE MEMORY ARRAYS
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Patent #:
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Issue Dt:
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02/21/2006
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Application #:
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10997345
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Filing Dt:
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11/24/2004
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Title:
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FULLY ISOLATED DIELECTRIC MEMORY CELL STRUCTURE FOR A DUAL BIT NITRIDE STORAGE DEVICE AND PROCESS FOR MAKING SAME
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|
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Patent #:
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NONE
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Issue Dt:
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Application #:
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11000685
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Filing Dt:
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12/01/2004
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Publication #:
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Pub Dt:
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06/01/2006
| | | | |
Title:
|
Polymer-based transistor devices, methods, and systems
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Patent #:
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|
Issue Dt:
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11/28/2006
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Application #:
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11000740
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Filing Dt:
|
12/01/2004
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Title:
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SELECTIVE POLYMER GROWTH FOR MEMORY CELL FABRICATION
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|
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Patent #:
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|
Issue Dt:
|
10/30/2007
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Application #:
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11000870
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Filing Dt:
|
12/01/2004
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Title:
|
METAL/OXIDE ETCH AFTER POLISH TO PREVENT BRIDGING BETWEEN ADJACENT FEATURES OF A SEMICONDUCTOR STRUCTURE
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|
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Patent #:
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|
Issue Dt:
|
06/24/2008
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Application #:
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11001519
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Filing Dt:
|
12/01/2004
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Title:
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MEMORY DEVICE WITH A SELECTION ELEMENT AND A CONTROL LINE IN A SUBSTANTIALLY SIMILAR LAYER
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|
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Patent #:
|
|
Issue Dt:
|
09/18/2007
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Application #:
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11001940
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Filing Dt:
|
12/01/2004
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Title:
|
METHOD, SYSTEM, AND CIRCUIT FOR PERFORMING A MEMORY RELATED OPERATION
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|
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Patent #:
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|
Issue Dt:
|
10/17/2006
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Application #:
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11003208
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Filing Dt:
|
12/02/2004
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Title:
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METHOD FOR ACHIEVING INCREASED CONTROL OVER INTERCONNECT LINE THICKNESS ACROSS A WAFER AND BETWEEN WAFERS
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|
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Patent #:
|
|
Issue Dt:
|
07/15/2008
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Application #:
|
11003528
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Filing Dt:
|
12/03/2004
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Title:
|
HIGH-VOLTAGE TRANSISTOR HAVING A U-SHAPED GATE AND METHOD FOR FORMING SAME
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|
|
Patent #:
|
|
Issue Dt:
|
05/30/2006
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Application #:
|
11003574
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Filing Dt:
|
12/03/2004
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Title:
|
METHOD FOR FORMING WORDLINES HAVING IRREGULAR SPACING IN A MEMORY ARRAY
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|
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Patent #:
|
|
Issue Dt:
|
04/29/2008
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Application #:
|
11008233
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Filing Dt:
|
12/10/2004
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Title:
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MEMORY CELL HAVING ENHANCED HIGH-K DIELECTRIC
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|
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Patent #:
|
|
Issue Dt:
|
07/04/2006
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Application #:
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11008263
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Filing Dt:
|
12/10/2004
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Title:
|
ONE STACK WITH STEAM OXIDE FOR CHARGE RETENTION
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|
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Patent #:
|
|
Issue Dt:
|
09/05/2006
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Application #:
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11021681
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Filing Dt:
|
12/23/2004
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Title:
|
MEMORY ELEMENTS USING ORGANIC ACTIVE LAYER
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|
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Patent #:
|
|
Issue Dt:
|
11/11/2008
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Application #:
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11021944
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Filing Dt:
|
12/23/2004
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Title:
|
UTILIZATION OF MEMORY-DIODE WHICH MAY HAVE EACH OF A PLURALITY OF DIFFERENT MEMORY STATES
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|
|
Patent #:
|
|
Issue Dt:
|
05/27/2008
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Application #:
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11021958
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Filing Dt:
|
12/23/2004
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Publication #:
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Pub Dt:
|
06/29/2006
| | | | |
Title:
|
METHOD OF PROGRAMMING, READING AND ERASING MEMORY-DIODE IN A MEMORY-DIODE ARRAY
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|
|
Patent #:
|
|
Issue Dt:
|
04/24/2007
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Application #:
|
11021959
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Filing Dt:
|
12/23/2004
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Title:
|
MEMORY ELEMENT WITH NITROGEN-CONTAINING ACTIVE LAYER
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|
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Patent #:
|
|
Issue Dt:
|
07/08/2008
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Application #:
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11023914
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Filing Dt:
|
12/28/2004
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Title:
|
CURRENT SENSING ARCHITECTURE FOR HIGH BITLINE VOLTAGE, RAIL TO RAIL OUTPUT SWING AND VCC NOISE CANCELLATION
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|
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Patent #:
|
|
Issue Dt:
|
12/25/2007
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Application #:
|
11024257
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Filing Dt:
|
12/28/2004
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Publication #:
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Pub Dt:
|
06/29/2006
| | | | |
Title:
|
SENSE AMPLIFIERS WITH HIGH VOLTAGE SWING
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|
|
Patent #:
|
|
Issue Dt:
|
02/27/2007
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Application #:
|
11026105
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Filing Dt:
|
12/30/2004
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Title:
|
REVERSIBLE FIELD-PROGRAMMABLE ELECTRIC INTERCONNECTS
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|
|
Patent #:
|
|
Issue Dt:
|
11/15/2005
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Application #:
|
11029454
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Filing Dt:
|
01/06/2005
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Publication #:
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|
Pub Dt:
|
06/02/2005
| | | | |
Title:
|
SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE CONTROL METHOD
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|
|
Patent #:
|
|
Issue Dt:
|
02/28/2012
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Application #:
|
11033588
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Filing Dt:
|
01/12/2005
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Publication #:
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|
Pub Dt:
|
07/13/2006
| | | | |
Title:
|
MEMORY DEVICE HAVING TRAPEZOIDAL BITLINES AND METHOD OF FABRICATING SAME
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|
|
Patent #:
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|
Issue Dt:
|
08/01/2006
|
Application #:
|
11033653
|
Filing Dt:
|
01/12/2005
|
Title:
|
USE OF TA-CAPPED METAL LINE TO IMPROVE FORMATION OF MEMORY ELEMENT FILMS
|
|