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Reel/Frame:024522/0338   Pages: 225
Recorded: 06/04/2010
Attorney Dkt #:042243-0080
Conveyance: SECURITY AGREEMENT
Total properties: 1906
Page 12 of 20
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
Patent #:
Issue Dt:
10/10/2006
Application #:
10841850
Filing Dt:
05/07/2004
Title:
FLASH MEMORY CELL AND METHODS FOR PROGRAMMING AND ERASING
2
Patent #:
Issue Dt:
12/13/2005
Application #:
10841933
Filing Dt:
05/06/2004
Title:
STRUCTURE AND METHOD FOR PROTECTING MEMORY CELLS FROM UV RADIATION DAMAGE AND UV RADIATION-INDUCED CHARGING DURING BACKEND PROCESSING
3
Patent #:
Issue Dt:
01/24/2006
Application #:
10843289
Filing Dt:
05/11/2004
Publication #:
Pub Dt:
11/17/2005
Title:
BITLINE IMPLANT UTILIZING DUAL POLY
4
Patent #:
Issue Dt:
04/26/2005
Application #:
10844116
Filing Dt:
05/12/2004
Title:
CASCODE AMPLIFIER CIRCUIT FOR GENERATING AND MAINTAINING A FAST, STABLE AND ACCURATE BIT LINE VOLTAGE
5
Patent #:
Issue Dt:
12/27/2005
Application #:
10848679
Filing Dt:
05/19/2004
Publication #:
Pub Dt:
11/04/2004
Title:
STACKED ORGANIC MEMORY DEVICES AND METHODS OF OPERATING AND FABRICATING
6
Patent #:
Issue Dt:
12/19/2006
Application #:
10859369
Filing Dt:
06/01/2004
Title:
METHOD AND DEVICE FOR REDUCING INTERFACE AREA OF A MEMORY DEVICE
7
Patent #:
Issue Dt:
03/07/2006
Application #:
10860450
Filing Dt:
06/03/2004
Title:
METHOD OF DETERMINING VOLTAGE COMPENSATION FOR FLASH MEMORY DEVICES
8
Patent #:
Issue Dt:
08/15/2006
Application #:
10861437
Filing Dt:
06/03/2004
Title:
UV-BLOCKING ETCH STOP LAYER FOR REDUCING UV-INDUCED CHARGING OF CHARGE STORAGE LAYER IN MEMORY DEVICES IN BEOL PROCESSING
9
Patent #:
Issue Dt:
06/05/2007
Application #:
10861575
Filing Dt:
06/04/2004
Title:
METHOD AND SYSTEM FOR IMPROVING THE TOPOGRAPHY OF A MEMORY ARRAY
10
Patent #:
Issue Dt:
02/13/2007
Application #:
10862636
Filing Dt:
06/07/2004
Title:
LDC IMPLANT FOR MIRRORBIT TO IMPROVE VT ROLL-OFF AND FORM SHARPER JUNCTION
11
Patent #:
Issue Dt:
12/21/2004
Application #:
10863673
Filing Dt:
06/08/2004
Title:
MEMORY DEVICE AND METHODS OF USING NEGATIVE GATE STRESS TO CORRECT OVER-ERASED MEMORY CELLS
12
Patent #:
Issue Dt:
08/23/2005
Application #:
10863933
Filing Dt:
06/09/2004
Title:
RAMP SOURCE HOT-HOLE PROGRAMMING FOR TRAP BASED NON-VOLATILE MEMORY DEVICES
13
Patent #:
Issue Dt:
05/30/2006
Application #:
10864142
Filing Dt:
06/08/2004
Title:
MEMORY WORDLINE SPACER
14
Patent #:
Issue Dt:
07/31/2007
Application #:
10864947
Filing Dt:
06/10/2004
Publication #:
Pub Dt:
12/15/2005
Title:
ERASE ALGORITHM FOR MULTI-LEVEL BIT FLASH MEMORY
15
Patent #:
Issue Dt:
08/29/2006
Application #:
10869286
Filing Dt:
06/16/2004
Title:
ALIGNMENT MARKS WITH SALICIDED SPACERS BETWEEN BITLINES FOR ALIGNMENT SIGNAL IMPROVEMENT
16
Patent #:
Issue Dt:
02/07/2006
Application #:
10869774
Filing Dt:
06/16/2004
Title:
SEMICONDUCTOR DEVICE WITH CORE AND PERIPHERY REGIONS
17
Patent #:
Issue Dt:
12/05/2006
Application #:
10873069
Filing Dt:
06/21/2004
Title:
ELECTRICALLY ADDRESSABLE MEMORY SWITCH
18
Patent #:
Issue Dt:
02/07/2006
Application #:
10878091
Filing Dt:
06/28/2004
Publication #:
Pub Dt:
11/25/2004
Title:
MEMORY DEVICE HAVING A P+ GATE AND THIN BOTTOM OXIDE AND METHOD OF ERASING SAME
19
Patent #:
Issue Dt:
09/13/2005
Application #:
10882538
Filing Dt:
06/30/2004
Publication #:
Pub Dt:
12/09/2004
Title:
CONTROL OF MEMORY ARRAYS UTILIZING ZENER DIODE-LIKE DEVICES
20
Patent #:
Issue Dt:
01/02/2007
Application #:
10883350
Filing Dt:
07/01/2004
Publication #:
Pub Dt:
01/05/2006
Title:
SWITCHABLE MEMORY DIODE - A NEW MEMORY DEVICE
21
Patent #:
Issue Dt:
01/10/2006
Application #:
10883924
Filing Dt:
07/01/2004
Title:
FLOATING GATE SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE
22
Patent #:
Issue Dt:
01/17/2006
Application #:
10885268
Filing Dt:
07/06/2004
Publication #:
Pub Dt:
01/12/2006
Title:
METHOD OF IMPROVING ERASE VOLTAGE DISTRIBUTION FOR A FLASH MEMORY ARRAY HAVING DUMMY WORDLINES
23
Patent #:
Issue Dt:
07/04/2006
Application #:
10885284
Filing Dt:
07/06/2004
Title:
ARCHITECTURE FOR GENERATING ADAPTIVE ARBITRARY WAVEFORMS
24
Patent #:
Issue Dt:
05/17/2005
Application #:
10885944
Filing Dt:
07/07/2004
Title:
CUS FORMATION BY ANODIC SULFIDE PASSIVATION OF COPPER SURFACE
25
Patent #:
Issue Dt:
07/10/2007
Application #:
10887585
Filing Dt:
07/08/2004
Publication #:
Pub Dt:
01/12/2006
Title:
BOND PAD STRUCTURE FOR COPPER METALLIZATION HAVING INCREASED RELIABILITY AND METHOD FOR FABRICATING SAME
26
Patent #:
Issue Dt:
03/28/2006
Application #:
10887782
Filing Dt:
07/09/2004
Title:
METHOD OF REFERENCE CELL DESIGN FOR OPTIMIZED MEMORY CIRCUIT YIELD
27
Patent #:
Issue Dt:
11/29/2005
Application #:
10889424
Filing Dt:
07/12/2004
Title:
ONO FABRICATION PROCESS FOR REDUCING OXYGEN VACANCY CONTENT IN BOTTOM OXIDE LAYER IN FLASH MEMORY DEVICES
28
Patent #:
Issue Dt:
09/09/2008
Application #:
10896292
Filing Dt:
07/20/2004
Title:
APPARATUS AND METHOD FOR A MEMORY ARRAY WITH SHALLOW TRENCH ISOLATION REGIONS BETWEEN BIT LINES FOR INCREASED PROCESS MARGINS
29
Patent #:
Issue Dt:
07/18/2006
Application #:
10896299
Filing Dt:
07/20/2004
Title:
METHOD FOR PROGRAMMING DUAL BIT MEMORY DEVICES TO REDUCE COMPLEMENTARY BIT DISTURBANCE
30
Patent #:
Issue Dt:
05/09/2006
Application #:
10896651
Filing Dt:
07/22/2004
Title:
METHOD OF PROGRAMMING A FLASH MEMORY DEVICE USING MULTILEVEL CHARGE STORAGE
31
Patent #:
Issue Dt:
12/11/2007
Application #:
10899344
Filing Dt:
07/26/2004
Title:
THREE DIMENSIONAL POLYMER MEMORY CELL SYSTEMS
32
Patent #:
Issue Dt:
08/15/2006
Application #:
10899684
Filing Dt:
07/26/2004
Title:
METHOD FOR PULSE ERASE IN DUAL BIT MEMORY DEVICES
33
Patent #:
Issue Dt:
01/02/2007
Application #:
10899873
Filing Dt:
07/27/2004
Publication #:
Pub Dt:
06/02/2005
Title:
MOLECULAR MEMORY DEVICE
34
Patent #:
Issue Dt:
06/20/2006
Application #:
10900832
Filing Dt:
07/28/2004
Title:
METHODS OF DETERMINING CHARACTERISTICS OF DOPED REGIONS ON DEVICE WAFERS, AND SYSTEM FOR ACCOMPLISHING SAME
35
Patent #:
Issue Dt:
05/09/2006
Application #:
10909693
Filing Dt:
08/02/2004
Publication #:
Pub Dt:
02/02/2006
Title:
FLASH MEMORY UNIT AND METHOD OF PROGRAMMING A FLASH MEMORY DEVICE
36
Patent #:
Issue Dt:
01/30/2007
Application #:
10915771
Filing Dt:
08/11/2004
Publication #:
Pub Dt:
02/16/2006
Title:
MEMORY CELL WITH REDUCED DIBL AND VSS RESISTANCE
37
Patent #:
Issue Dt:
03/24/2009
Application #:
10916167
Filing Dt:
08/11/2004
Publication #:
Pub Dt:
02/16/2006
Title:
METHOD OF FORMING NARROWLY SPACED FLASH MEMORY CONTACT OPENINGS AND LITHOGRAPHY MASKS
38
Patent #:
Issue Dt:
01/02/2007
Application #:
10917562
Filing Dt:
08/13/2004
Title:
USING THIN UNDOPED TEOS WITH BPTEOS ILD OR BPTEOS ILD ALONE TO IMPROVE CHARGE LOSS AND CONTACT RESISTANCE IN MULTI BIT MEMORY DEVICES
39
Patent #:
Issue Dt:
12/20/2005
Application #:
10919119
Filing Dt:
08/16/2004
Title:
TEST STRUCTURE FOR CHARACTERIZING JUNCTION LEAKAGE CURRENT
40
Patent #:
Issue Dt:
04/03/2007
Application #:
10919572
Filing Dt:
08/17/2004
Publication #:
Pub Dt:
02/23/2006
Title:
POLYMER MEMORY DEVICE WITH VARIABLE PERIOD OF RETENTION TIME
41
Patent #:
Issue Dt:
10/30/2007
Application #:
10919846
Filing Dt:
08/17/2004
Publication #:
Pub Dt:
02/23/2006
Title:
SYSTEMS AND METHODS FOR ADJUSTING PROGRAMMING THRESHOLDS OF POLYMER MEMORY CELLS
42
Patent #:
Issue Dt:
10/17/2006
Application #:
10919872
Filing Dt:
08/17/2004
Title:
METHOD TO IMPROVE YIELD AND SIMPLIFY OPERATION OF POLYMER MEMORY CELLS
43
Patent #:
NONE
Issue Dt:
Application #:
10928354
Filing Dt:
08/27/2004
Publication #:
Pub Dt:
03/02/2006
Title:
Deposition of hard-mask with minimized hillocks and bubbles
44
Patent #:
Issue Dt:
12/19/2006
Application #:
10928582
Filing Dt:
08/27/2004
Title:
SONOS MEMORY WITH INVERSION BIT-LINES
45
Patent #:
Issue Dt:
08/05/2008
Application #:
10928665
Filing Dt:
08/27/2004
Title:
SEMICONDUCTOR COMPONENT HAVING A CONTACT STRUCTURE AND METHOD OF MANUFACTURE
46
Patent #:
Issue Dt:
09/05/2006
Application #:
10933588
Filing Dt:
09/03/2004
Title:
SYSTEM AND METHOD FOR MULTI-BIT FLASH READS USING DUAL DYNAMIC REFERENCES
47
Patent #:
Issue Dt:
08/11/2009
Application #:
10934828
Filing Dt:
09/02/2004
Title:
SEMICONDUCTOR FORMATION METHOD THAT UTILIZES MULTIPLE ETCH STOP LAYERS
48
Patent #:
Issue Dt:
04/22/2008
Application #:
10934923
Filing Dt:
09/02/2004
Title:
SEMICONDUCTOR CONTACT AND NITRIDE SPACER FORMATION SYSTEM AND METHOD
49
Patent #:
NONE
Issue Dt:
Application #:
10935301
Filing Dt:
09/07/2004
Publication #:
Pub Dt:
03/09/2006
Title:
Vertical JFET as used for selective component in a memory array
50
Patent #:
Issue Dt:
10/31/2006
Application #:
10939773
Filing Dt:
09/13/2004
Title:
METHOD AND STRUCTURE OF MEMORY ELEMENT PLUG WITH CONDUCTIVE TA REMOVED FROM SIDEWALL AT REGION OF MEMORY ELEMENT FILM
51
Patent #:
Issue Dt:
11/14/2006
Application #:
10939775
Filing Dt:
09/13/2004
Title:
METHOD OF MAKING A SEMICONDUCTOR STRUCTURE
52
Patent #:
Issue Dt:
12/12/2006
Application #:
10939897
Filing Dt:
09/13/2004
Title:
METHOD OF FORMING COPPER SULFIDE LAYER OVER SUBSTRATE
53
Patent #:
Issue Dt:
07/18/2006
Application #:
10945914
Filing Dt:
09/22/2004
Title:
METHODS AND SYSTEMS FOR REDUCING ERASE TIMES IN FLASH MEMORY DEVICES
54
Patent #:
Issue Dt:
05/02/2006
Application #:
10946809
Filing Dt:
09/22/2004
Publication #:
Pub Dt:
03/23/2006
Title:
READ APPROACH FOR MULTI-LEVEL VIRTUAL GROUND MEMORY
55
Patent #:
Issue Dt:
08/19/2008
Application #:
10946812
Filing Dt:
09/22/2004
Title:
PAGE_ EXE ERASE ALGORITHM FOR FLASH MEMORY
56
Patent #:
Issue Dt:
04/12/2005
Application #:
10951370
Filing Dt:
09/28/2004
Publication #:
Pub Dt:
03/03/2005
Title:
PHOTOSENSITIVE POLYMERIC MEMORY ELEMENTS
57
Patent #:
Issue Dt:
06/27/2006
Application #:
10951410
Filing Dt:
09/28/2004
Title:
SYSTEM THAT FACILITATES READING MULTI-LEVEL DATA IN NON-VOLATILE MEMORY
58
Patent #:
Issue Dt:
10/03/2006
Application #:
10957247
Filing Dt:
10/01/2004
Title:
SO2 TREATMENT OF OXIDIZED CUO FOR COPPER SULFIDE FORMATION OF MEMORY ELEMENT GROWTH
59
Patent #:
Issue Dt:
11/13/2007
Application #:
10958044
Filing Dt:
10/04/2004
Title:
MEMORY DEVICE WITH A SELF-ASSEMBLED POLYMER FILM AND METHOD OF MAKING THE SAME
60
Patent #:
Issue Dt:
04/17/2007
Application #:
10968414
Filing Dt:
10/19/2004
Title:
NON-VOLATILE MEMORY SYSTEM HAVING A PROGRAMMABLY SELECTABLE BOOT CODE SECTION SIZE
61
Patent #:
Issue Dt:
06/27/2006
Application #:
10968705
Filing Dt:
10/19/2004
Title:
ION PATH POLYMERS FOR ION-MOTION MEMORY
62
Patent #:
Issue Dt:
03/28/2006
Application #:
10968713
Filing Dt:
10/19/2004
Title:
PATTERNING FOR ELONGATED VSS CONTACT FLASH MEMORY
63
Patent #:
NONE
Issue Dt:
Application #:
10975629
Filing Dt:
10/28/2004
Publication #:
Pub Dt:
05/04/2006
Title:
System and method for improved memory performance in a mobile device
64
Patent #:
Issue Dt:
10/06/2009
Application #:
10976760
Filing Dt:
11/01/2004
Title:
FLASH MEMORY DEVICE HAVING INCREASED OVER-ERASE CORRECTION EFFICIENCY AND ROBUSTNESS AGAINST DEVICE VARIATIONS
65
Patent #:
Issue Dt:
07/22/2008
Application #:
10976816
Filing Dt:
11/01/2004
Publication #:
Pub Dt:
05/04/2006
Title:
SYSTEM AND METHOD FOR PROTECTING SEMICONDUCTOR DEVICES
66
Patent #:
Issue Dt:
06/26/2007
Application #:
10976876
Filing Dt:
11/01/2004
Title:
SEMICONDUCTOR DEVICE WITH ELECTRICALLY BIASED DIE EDGE SEAL
67
Patent #:
Issue Dt:
05/22/2007
Application #:
10978621
Filing Dt:
11/01/2004
Title:
POLYMER MEMORY CELL OPERATION
68
Patent #:
Issue Dt:
05/20/2008
Application #:
10978845
Filing Dt:
11/01/2004
Title:
METHOD OF MAKING AN ORGANIC MEMORY CELL
69
Patent #:
Issue Dt:
11/28/2006
Application #:
10979516
Filing Dt:
11/02/2004
Title:
METHOD OF MAKING A MEMORY CELL
70
Patent #:
Issue Dt:
01/15/2008
Application #:
10981026
Filing Dt:
11/04/2004
Title:
METHOD FOR ISOLATING A FAILURE SITE IN A WORDLINE IN A MEMORY ARRAY
71
Patent #:
Issue Dt:
12/19/2006
Application #:
10981174
Filing Dt:
11/04/2004
Title:
MEMORY CELL WITH PLASMA-GROWN OXIDE SPACER FOR REDUCED DIBL AND VSS RESISTANCE AND INCREASED RELIABILITY
72
Patent #:
Issue Dt:
03/28/2006
Application #:
10981833
Filing Dt:
11/04/2004
Title:
RAMPED SOFT PROGRAMMING FOR CONTROL OF ERASE VOLTAGE DISTRIBUTIONS IN FLASH MEMORY DEVICES
73
Patent #:
Issue Dt:
05/02/2006
Application #:
10982296
Filing Dt:
11/05/2004
Title:
MULTI BIT PROGRAM ALGORITHM
74
Patent #:
Issue Dt:
10/28/2008
Application #:
10983919
Filing Dt:
11/08/2004
Publication #:
Pub Dt:
03/30/2006
Title:
CONTROL OF MEMORY DEVICES POSSESSING VARIABLE RESISTANCE CHARACTERISTICS
75
Patent #:
Issue Dt:
04/03/2007
Application #:
10985172
Filing Dt:
11/10/2004
Title:
SYSTEMS AND METHODS FOR A MEMORY AND/OR SELECTION ELEMENT FORMED WITHIN A RECESS IN A METAL LINE
76
Patent #:
Issue Dt:
08/01/2006
Application #:
10986652
Filing Dt:
11/12/2004
Publication #:
Pub Dt:
04/28/2005
Title:
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
77
Patent #:
Issue Dt:
05/22/2007
Application #:
10987262
Filing Dt:
11/12/2004
Publication #:
Pub Dt:
05/18/2006
Title:
PROTECTION OF ACTIVE LAYERS OF MEMORY CELLS DURING PROCESSING OF OTHER ELEMENTS
78
Patent #:
Issue Dt:
06/19/2007
Application #:
10988239
Filing Dt:
11/12/2004
Title:
UTILIZATION OF A TA-CONTAINING CAP OVER COPPER TO FACILITATE CONCURRENT FORMATION OF COPPER VIAS AND MEMORY ELEMENT STRUCTURES
79
Patent #:
Issue Dt:
04/25/2006
Application #:
10990706
Filing Dt:
11/17/2004
Publication #:
Pub Dt:
05/18/2006
Title:
DIODE ARRAY ARCHITECTURE FOR ADDRESSING NANOSCALE RESISTIVE MEMORY ARRAYS
80
Patent #:
Issue Dt:
02/21/2006
Application #:
10997345
Filing Dt:
11/24/2004
Title:
FULLY ISOLATED DIELECTRIC MEMORY CELL STRUCTURE FOR A DUAL BIT NITRIDE STORAGE DEVICE AND PROCESS FOR MAKING SAME
81
Patent #:
NONE
Issue Dt:
Application #:
11000685
Filing Dt:
12/01/2004
Publication #:
Pub Dt:
06/01/2006
Title:
Polymer-based transistor devices, methods, and systems
82
Patent #:
Issue Dt:
11/28/2006
Application #:
11000740
Filing Dt:
12/01/2004
Title:
SELECTIVE POLYMER GROWTH FOR MEMORY CELL FABRICATION
83
Patent #:
Issue Dt:
10/30/2007
Application #:
11000870
Filing Dt:
12/01/2004
Title:
METAL/OXIDE ETCH AFTER POLISH TO PREVENT BRIDGING BETWEEN ADJACENT FEATURES OF A SEMICONDUCTOR STRUCTURE
84
Patent #:
Issue Dt:
06/24/2008
Application #:
11001519
Filing Dt:
12/01/2004
Title:
MEMORY DEVICE WITH A SELECTION ELEMENT AND A CONTROL LINE IN A SUBSTANTIALLY SIMILAR LAYER
85
Patent #:
Issue Dt:
09/18/2007
Application #:
11001940
Filing Dt:
12/01/2004
Title:
METHOD, SYSTEM, AND CIRCUIT FOR PERFORMING A MEMORY RELATED OPERATION
86
Patent #:
Issue Dt:
10/17/2006
Application #:
11003208
Filing Dt:
12/02/2004
Title:
METHOD FOR ACHIEVING INCREASED CONTROL OVER INTERCONNECT LINE THICKNESS ACROSS A WAFER AND BETWEEN WAFERS
87
Patent #:
Issue Dt:
07/15/2008
Application #:
11003528
Filing Dt:
12/03/2004
Title:
HIGH-VOLTAGE TRANSISTOR HAVING A U-SHAPED GATE AND METHOD FOR FORMING SAME
88
Patent #:
Issue Dt:
05/30/2006
Application #:
11003574
Filing Dt:
12/03/2004
Title:
METHOD FOR FORMING WORDLINES HAVING IRREGULAR SPACING IN A MEMORY ARRAY
89
Patent #:
Issue Dt:
04/29/2008
Application #:
11008233
Filing Dt:
12/10/2004
Title:
MEMORY CELL HAVING ENHANCED HIGH-K DIELECTRIC
90
Patent #:
Issue Dt:
07/04/2006
Application #:
11008263
Filing Dt:
12/10/2004
Title:
ONE STACK WITH STEAM OXIDE FOR CHARGE RETENTION
91
Patent #:
Issue Dt:
09/05/2006
Application #:
11021681
Filing Dt:
12/23/2004
Title:
MEMORY ELEMENTS USING ORGANIC ACTIVE LAYER
92
Patent #:
Issue Dt:
11/11/2008
Application #:
11021944
Filing Dt:
12/23/2004
Title:
UTILIZATION OF MEMORY-DIODE WHICH MAY HAVE EACH OF A PLURALITY OF DIFFERENT MEMORY STATES
93
Patent #:
Issue Dt:
05/27/2008
Application #:
11021958
Filing Dt:
12/23/2004
Publication #:
Pub Dt:
06/29/2006
Title:
METHOD OF PROGRAMMING, READING AND ERASING MEMORY-DIODE IN A MEMORY-DIODE ARRAY
94
Patent #:
Issue Dt:
04/24/2007
Application #:
11021959
Filing Dt:
12/23/2004
Title:
MEMORY ELEMENT WITH NITROGEN-CONTAINING ACTIVE LAYER
95
Patent #:
Issue Dt:
07/08/2008
Application #:
11023914
Filing Dt:
12/28/2004
Title:
CURRENT SENSING ARCHITECTURE FOR HIGH BITLINE VOLTAGE, RAIL TO RAIL OUTPUT SWING AND VCC NOISE CANCELLATION
96
Patent #:
Issue Dt:
12/25/2007
Application #:
11024257
Filing Dt:
12/28/2004
Publication #:
Pub Dt:
06/29/2006
Title:
SENSE AMPLIFIERS WITH HIGH VOLTAGE SWING
97
Patent #:
Issue Dt:
02/27/2007
Application #:
11026105
Filing Dt:
12/30/2004
Title:
REVERSIBLE FIELD-PROGRAMMABLE ELECTRIC INTERCONNECTS
98
Patent #:
Issue Dt:
11/15/2005
Application #:
11029454
Filing Dt:
01/06/2005
Publication #:
Pub Dt:
06/02/2005
Title:
SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE CONTROL METHOD
99
Patent #:
Issue Dt:
02/28/2012
Application #:
11033588
Filing Dt:
01/12/2005
Publication #:
Pub Dt:
07/13/2006
Title:
MEMORY DEVICE HAVING TRAPEZOIDAL BITLINES AND METHOD OF FABRICATING SAME
100
Patent #:
Issue Dt:
08/01/2006
Application #:
11033653
Filing Dt:
01/12/2005
Title:
USE OF TA-CAPPED METAL LINE TO IMPROVE FORMATION OF MEMORY ELEMENT FILMS
Assignors
1
Exec Dt:
05/10/2010
2
Exec Dt:
05/10/2010
3
Exec Dt:
05/10/2010
4
Exec Dt:
05/10/2010
Assignee
1
745 SEVENTH AVENUE
NEW YORK, NEW YORK 10019
Correspondence name and address
LATHAM & WATKINS, C/O JULIE DALKE
650 TOWN CENTER DR, 20TH FLOOR
042243-0080
COSTA MESA, CA 92626

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