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Reel/Frame:024522/0338   Pages: 225
Recorded: 06/04/2010
Attorney Dkt #:042243-0080
Conveyance: SECURITY AGREEMENT
Total properties: 1906
Page 17 of 20
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1
Patent #:
Issue Dt:
01/12/2010
Application #:
11750724
Filing Dt:
05/18/2007
Publication #:
Pub Dt:
09/27/2007
Title:
SELF ALIGNED MEMORY ELEMENT AND WORDLINE
2
Patent #:
Issue Dt:
08/14/2012
Application #:
11754877
Filing Dt:
05/29/2007
Publication #:
Pub Dt:
05/01/2008
Title:
SEQUENCE OF ALGORITHMS TO COMPUTE EQUILIBRIUM PRICES IN NETWORKS
3
Patent #:
Issue Dt:
07/28/2009
Application #:
11763510
Filing Dt:
06/15/2007
Publication #:
Pub Dt:
12/18/2008
Title:
PROCESS FOR MAKING A RESISTIVE MEMORY CELL WITH SEPARATELY PATTERNED ELECTRODES
4
Patent #:
Issue Dt:
03/29/2011
Application #:
11767620
Filing Dt:
06/25/2007
Publication #:
Pub Dt:
12/25/2008
Title:
FAULTY DANGLING METAL ROUTE DETECTION
5
Patent #:
Issue Dt:
05/12/2009
Application #:
11767622
Filing Dt:
06/25/2007
Publication #:
Pub Dt:
12/25/2008
Title:
COMPENSATION METHOD TO ACHIEVE UNIFORM PROGRAMMING SPEED OF FLASH MEMORY DEVICES
6
Patent #:
Issue Dt:
09/21/2010
Application #:
11767623
Filing Dt:
06/25/2007
Publication #:
Pub Dt:
12/25/2008
Title:
PROCESS APPLYING DIE ATTACH FILM TO SINGULATED DIE
7
Patent #:
NONE
Issue Dt:
Application #:
11770239
Filing Dt:
06/28/2007
Publication #:
Pub Dt:
01/01/2009
Title:
A semiconductor device for stacking dies in a multi-die chip packing using film over wire as well as multi-die chip devices that include film over wire
8
Patent #:
Issue Dt:
01/26/2010
Application #:
11771961
Filing Dt:
06/29/2007
Publication #:
Pub Dt:
07/03/2008
Title:
MULTI-LEVEL OPERATION IN DUAL ELEMENT CELLS USING A SUPPLEMENTAL PROGRAMMING LEVEL
9
Patent #:
NONE
Issue Dt:
Application #:
11781551
Filing Dt:
07/23/2007
Publication #:
Pub Dt:
11/15/2007
Title:
DEVICE HAVING A PROTECTIVE CAP FORMED OVER AN ANTI-REFLECTIVE COATING LAYER AND OVER AN INSULATING MATERIAL
10
Patent #:
Issue Dt:
09/28/2010
Application #:
11782507
Filing Dt:
07/24/2007
Publication #:
Pub Dt:
11/22/2007
Title:
SYSTEM AND METHOD FOR REDUCING PROCESS-INDUCED CHARGING
11
Patent #:
Issue Dt:
06/28/2011
Application #:
11788264
Filing Dt:
04/19/2007
Publication #:
Pub Dt:
10/23/2008
Title:
SELECTION OF A LOOKUP TABLE WITH DATA MASKED WITH A COMBINATION OF AN ADDITIVE AND MULTIPLICATIVE MASK
12
Patent #:
Issue Dt:
03/10/2009
Application #:
11789888
Filing Dt:
04/25/2007
Publication #:
Pub Dt:
11/01/2007
Title:
SEMICONDUCTOR DEVICE AND PROGRAMMING METHOD
13
Patent #:
Issue Dt:
12/23/2014
Application #:
11790305
Filing Dt:
04/24/2007
Publication #:
Pub Dt:
03/27/2008
Title:
EXHAUST SYSTEM
14
Patent #:
Issue Dt:
02/12/2013
Application #:
11796073
Filing Dt:
04/26/2007
Publication #:
Pub Dt:
10/30/2008
Title:
MEMORY DEVICE WITH IMPROVED PERFORMANCE
15
Patent #:
Issue Dt:
06/08/2010
Application #:
11796582
Filing Dt:
04/26/2007
Publication #:
Pub Dt:
10/30/2008
Title:
SELF-ALIGNED PATTERNING METHOD BY USING NON-CONFORMAL FILM AND ETCH BACK FOR FLASH MEMORY AND OTHER SEMICONDUCTOR APPLICATIONS
16
Patent #:
Issue Dt:
02/05/2013
Application #:
11801823
Filing Dt:
05/10/2007
Publication #:
Pub Dt:
11/13/2008
Title:
FLASH MEMORY CELL WITH A FLAIR GATE
17
Patent #:
NONE
Issue Dt:
Application #:
11804170
Filing Dt:
05/16/2007
Publication #:
Pub Dt:
11/20/2008
Title:
Self reference sensing system and method
18
Patent #:
Issue Dt:
06/30/2009
Application #:
11820278
Filing Dt:
06/18/2007
Publication #:
Pub Dt:
12/18/2008
Title:
DIE OFFSET DIE TO DIE BONDING
19
Patent #:
Issue Dt:
03/08/2011
Application #:
11821653
Filing Dt:
06/25/2007
Publication #:
Pub Dt:
12/25/2008
Title:
METHOD OF CONSTRUCTING A STACKED-DIE SEMICONDUCTOR STRUCTURE
20
Patent #:
NONE
Issue Dt:
Application #:
11829135
Filing Dt:
07/27/2007
Publication #:
Pub Dt:
01/29/2009
Title:
FUEL CELL USING DEUTERIUM
21
Patent #:
Issue Dt:
05/19/2009
Application #:
11834420
Filing Dt:
08/06/2007
Publication #:
Pub Dt:
02/12/2009
Title:
READING MULTI-CELL MEMORY DEVICES UTILIZING COMPLEMENTARY BIT INFORMATION
22
Patent #:
Issue Dt:
08/17/2010
Application #:
11835538
Filing Dt:
08/08/2007
Publication #:
Pub Dt:
02/12/2009
Title:
USE OF A POLYMER SPACER AND SI TRENCH IN A BITLINE JUNCTION OF A FLASH MEMORY CELL TO IMPROVE TPD CHARACTERISTICS
23
Patent #:
Issue Dt:
09/06/2011
Application #:
11835542
Filing Dt:
08/08/2007
Publication #:
Pub Dt:
02/12/2009
Title:
ORO AND ORPRO WITH BIT LINE TRENCH TO SUPPRESS TRANSPORT PROGRAM DISTURB
24
Patent #:
NONE
Issue Dt:
Application #:
11835545
Filing Dt:
08/08/2007
Publication #:
Pub Dt:
09/25/2008
Title:
SINGULATED BARE DIE TESTING
25
Patent #:
Issue Dt:
07/07/2009
Application #:
11837949
Filing Dt:
08/13/2007
Publication #:
Pub Dt:
02/19/2009
Title:
EFFICIENT AND SYSTEMATIC MEASUREMENT FLOW ON DRAIN VOLTAGE FOR DIFFERENT TRIMMING IN FLASH SILICON CHARACTERIZATION
26
Patent #:
Issue Dt:
07/07/2009
Application #:
11837976
Filing Dt:
08/13/2007
Publication #:
Pub Dt:
02/19/2009
Title:
REGULATION OF BOOST-STRAP NODE RAMP RATE USING CAPACITANCE TO COUNTER PARASITIC ELEMENTS IN CHANNEL
27
Patent #:
Issue Dt:
07/06/2010
Application #:
11838483
Filing Dt:
08/14/2007
Publication #:
Pub Dt:
02/19/2009
Title:
CAPACITOR STRUCTURE USED FOR FLASH MEMORY
28
Patent #:
NONE
Issue Dt:
Application #:
11842655
Filing Dt:
08/21/2007
Publication #:
Pub Dt:
02/26/2009
Title:
DIE STACKING IN MULTI-DIE STACKS USING DIE SUPPORT MECHANISMS
29
Patent #:
NONE
Issue Dt:
Application #:
11844518
Filing Dt:
08/24/2007
Publication #:
Pub Dt:
02/26/2009
Title:
PROCESS OF FORMING AN ELECTRONIC DEVICE INCLUDING DEPOSITING LAYERS WITHIN OPENINGS
30
Patent #:
Issue Dt:
07/19/2011
Application #:
11847507
Filing Dt:
08/30/2007
Publication #:
Pub Dt:
03/05/2009
Title:
SACRIFICIAL NITRIDE AND GATE REPLACEMENT
31
Patent #:
Issue Dt:
07/20/2010
Application #:
11847986
Filing Dt:
08/30/2007
Publication #:
Pub Dt:
04/03/2008
Title:
MAIN MEMORY IN A SYSTEM WITH A MEMORY CONTROLLER CONFIGURED TO CONTROL ACCESS TO NON-VOLATILE MEMORY, AND RELATED TECHNOLOGIES
32
Patent #:
Issue Dt:
07/20/2010
Application #:
11848013
Filing Dt:
08/30/2007
Publication #:
Pub Dt:
04/03/2008
Title:
SYSTEMS AND APPARATUS FOR MAIN MEMORY WITH NON-VOLATILE TYPE MEMORY MODULES, AND RELATED TECHNOLOGIES
33
Patent #:
Issue Dt:
07/20/2010
Application #:
11848040
Filing Dt:
08/30/2007
Publication #:
Pub Dt:
04/03/2008
Title:
METHODS FOR MAIN MEMORY WITH NON-VOLATILE TYPE MEMORY MODULES, AND RELATED TECHNOLOGIES
34
Patent #:
Issue Dt:
07/20/2010
Application #:
11848083
Filing Dt:
08/30/2007
Publication #:
Pub Dt:
04/03/2008
Title:
METHODS FOR MAIN MEMORY IN A SYSTEM WITH A MEMORY CONTROLLER CONFIGURED TO CONTROL ACCESS TO NON-VOLATILE MEMORY, AND RELATED TECHNOLOGIES
35
Patent #:
Issue Dt:
06/04/2013
Application #:
11848515
Filing Dt:
08/31/2007
Publication #:
Pub Dt:
03/05/2009
Title:
GATE REPLACEMENT WITH TOP OXIDE REGROWTH FOR THE TOP OXIDE IMPROVEMENT
36
Patent #:
Issue Dt:
03/11/2014
Application #:
11852644
Filing Dt:
09/10/2007
Publication #:
Pub Dt:
03/12/2009
Title:
CRYPTOGRAPHIC SYSTEM WITH MODULAR RANDOMIZATION OF EXPONENTIATION
37
Patent #:
Issue Dt:
08/11/2009
Application #:
11855704
Filing Dt:
09/14/2007
Title:
BACK-TO-BACK NPN/PNP PROTECTION DIODES
38
Patent #:
Issue Dt:
03/20/2012
Application #:
11870102
Filing Dt:
10/10/2007
Publication #:
Pub Dt:
04/16/2009
Title:
RANDOMIZED RSA-BASED CRYPTOGRAPHIC EXPONENTIATION RESISTANT TO SIDE CHANNEL AND FAULT ATTACKS
39
Patent #:
Issue Dt:
12/08/2009
Application #:
11872989
Filing Dt:
10/16/2007
Publication #:
Pub Dt:
04/16/2009
Title:
CONTROLLED RAMP RATES FOR METAL BITLINES DURING WRITE OPERATIONS FROM HIGH VOLTAGE DRIVER FOR MEMORY APPLICATIONS
40
Patent #:
Issue Dt:
10/15/2013
Application #:
11873810
Filing Dt:
10/17/2007
Publication #:
Pub Dt:
04/23/2009
Title:
HYBRID FLASH MEMORY DEVICE
41
Patent #:
Issue Dt:
11/09/2010
Application #:
11873822
Filing Dt:
10/17/2007
Publication #:
Pub Dt:
04/23/2009
Title:
SPLIT CHARGE STORAGE NODE INNER SPACER PROCESS
42
Patent #:
Issue Dt:
09/13/2011
Application #:
11873824
Filing Dt:
10/17/2007
Publication #:
Pub Dt:
04/23/2009
Title:
PHOTOVOLTAIC THIN COATING FOR COLLECTOR GENERATOR
43
Patent #:
Issue Dt:
05/17/2011
Application #:
11873980
Filing Dt:
10/17/2007
Publication #:
Pub Dt:
04/23/2009
Title:
TAMPER REACTIVE MEMORY DEVICE TO SECURE DATA FROM TAMPER ATTACKS
44
Patent #:
Issue Dt:
04/05/2011
Application #:
11874001
Filing Dt:
10/17/2007
Publication #:
Pub Dt:
04/23/2009
Title:
OPTIMIZE PERSONALIZATION CONDITIONS FOR ELECTRONIC DEVICE TRANSMISSION RATES WITH INCREASED TRANSMITTING FREQUENCY
45
Patent #:
Issue Dt:
06/12/2012
Application #:
11874036
Filing Dt:
10/17/2007
Publication #:
Pub Dt:
04/23/2009
Title:
SECURE PERSONALIZATION OF MEMORY-BASED ELECTRONIC DEVICES
46
Patent #:
Issue Dt:
02/02/2010
Application #:
11874076
Filing Dt:
10/17/2007
Publication #:
Pub Dt:
04/23/2009
Title:
FAST SINGLE PHASE PROGRAM ALGORITHM FOR QUADBIT
47
Patent #:
Issue Dt:
10/30/2012
Application #:
11877497
Filing Dt:
10/23/2007
Publication #:
Pub Dt:
04/23/2009
Title:
LOW-DENSITY PARITY-CHECK CODE BASED ERROR CORRECTION FOR MEMORY DEVICE
48
Patent #:
Issue Dt:
08/12/2008
Application #:
11878296
Filing Dt:
07/23/2007
Publication #:
Pub Dt:
11/15/2007
Title:
SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
49
Patent #:
Issue Dt:
07/21/2009
Application #:
11879989
Filing Dt:
07/18/2007
Publication #:
Pub Dt:
02/28/2008
Title:
NONVOLATILE STORAGE AND ERASE CONTROL
50
Patent #:
Issue Dt:
04/29/2014
Application #:
11881969
Filing Dt:
07/30/2007
Publication #:
Pub Dt:
02/05/2009
Title:
CONTACT CONFIGURATION FOR UNDERTAKING TESTS ON CIRCUIT BOARD
51
Patent #:
Issue Dt:
02/08/2011
Application #:
11886139
Filing Dt:
03/13/2008
Publication #:
Pub Dt:
08/14/2008
Title:
IC CARRIER, IC SOCKET AND METHOD FOR TESTING IC DEVICE
52
Patent #:
Issue Dt:
01/05/2010
Application #:
11894828
Filing Dt:
08/22/2007
Publication #:
Pub Dt:
12/20/2007
Title:
CARRIER FOR STACKED TYPE SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
53
Patent #:
Issue Dt:
09/25/2012
Application #:
11894921
Filing Dt:
08/22/2007
Publication #:
Pub Dt:
12/20/2007
Title:
EXPOSURE SYSTEM, SEMICONDUCTOR DEVICE, AND METHOD FOR FABRICATING THE SEMICONDUCTOR DEVICE
54
Patent #:
Issue Dt:
07/20/2010
Application #:
11895901
Filing Dt:
08/28/2007
Publication #:
Pub Dt:
03/05/2009
Title:
METHOD AND STRUCTURE OF MINIMIZING MOLD BLEEDING ON A SUBSTRATE SURFACE OF A SEMICONDUCTOR PACKAGE
55
Patent #:
NONE
Issue Dt:
Application #:
11899575
Filing Dt:
09/06/2007
Publication #:
Pub Dt:
03/12/2009
Title:
Ta-lined tungsten plugs for transistor-local hydrogen gathering
56
Patent #:
Issue Dt:
02/03/2015
Application #:
11899597
Filing Dt:
09/06/2007
Publication #:
Pub Dt:
03/12/2009
Title:
Method of forming controllably conductive oxide
57
Patent #:
Issue Dt:
02/08/2011
Application #:
11924169
Filing Dt:
10/25/2007
Publication #:
Pub Dt:
04/30/2009
Title:
SPLIT CHARGE STORAGE NODE OUTER SPACER PROCESS
58
Patent #:
Issue Dt:
04/06/2010
Application #:
11924823
Filing Dt:
10/26/2007
Publication #:
Pub Dt:
04/30/2009
Title:
SELECTIVE SILICIDE FORMATION USING RESIST ETCHBACK
59
Patent #:
Issue Dt:
01/28/2014
Application #:
11928372
Filing Dt:
10/30/2007
Publication #:
Pub Dt:
04/30/2009
Title:
SIGNAL DESCRAMBLING DETECTOR
60
Patent #:
Issue Dt:
08/07/2012
Application #:
11928434
Filing Dt:
10/30/2007
Publication #:
Pub Dt:
04/30/2009
Title:
ERROR CORRECTION CODING IN FLASH MEMORY DEVICES
61
Patent #:
Issue Dt:
11/01/2011
Application #:
11928864
Filing Dt:
10/30/2007
Publication #:
Pub Dt:
05/22/2008
Title:
FUEL CELL STACK STRUCTURE
62
Patent #:
Issue Dt:
09/09/2014
Application #:
11928865
Filing Dt:
10/30/2007
Publication #:
Pub Dt:
04/30/2009
Title:
NON-VOLATILE MEMORY ARRAY PARTITIONING ARCHITECTURE AND METHOD TO UTILIZE SINGLE LEVEL CELLS AND MULTI-LEVEL CELLS WITHIN THE SAME MEMORY
63
Patent #:
Issue Dt:
08/03/2010
Application #:
11929097
Filing Dt:
10/30/2007
Publication #:
Pub Dt:
04/30/2009
Title:
CONTROL OF TEMPERATURE SLOPE FOR BAND GAP REFERENCE VOLTAGE IN A MEMORY DEVICE
64
Patent #:
Issue Dt:
07/28/2009
Application #:
11929724
Filing Dt:
10/30/2007
Publication #:
Pub Dt:
04/30/2009
Title:
NONVOLATILE MEMORY ARRAY ARCHITECTURE
65
Patent #:
Issue Dt:
02/22/2011
Application #:
11929741
Filing Dt:
10/30/2007
Publication #:
Pub Dt:
04/30/2009
Title:
DETERMINISTIC PROGRAMMING ALGORITHM THAT PROVIDES TIGHTER CELL DISTRIBUTIONS WITH A REDUCED NUMBER OF PROGRAMMING PULSES
66
Patent #:
Issue Dt:
08/09/2011
Application #:
11929761
Filing Dt:
10/30/2007
Publication #:
Pub Dt:
04/30/2009
Title:
MEMORY ARRAY OF PAIRS OF NONVOLATILE MEMORY CELLS USING FOWLER-NORDHEIM PROGRAMMING AND ERASING
67
Patent #:
Issue Dt:
11/18/2008
Application #:
11931992
Filing Dt:
10/31/2007
Publication #:
Pub Dt:
02/28/2008
Title:
FLASH MEMORY DEVICE HAVING IMPROVED PROGRAM RATE
68
Patent #:
Issue Dt:
03/29/2011
Application #:
11934628
Filing Dt:
11/02/2007
Publication #:
Pub Dt:
05/07/2009
Title:
PROCESSES FOR FORMING ELECTRONIC DEVICES INCLUDING POLISHING METAL-CONTAINING LAYERS
69
Patent #:
Issue Dt:
11/03/2009
Application #:
11935049
Filing Dt:
11/05/2007
Publication #:
Pub Dt:
05/07/2009
Title:
DECODING SYSTEM CAPABLE OF REDUCING SECTOR SELECT AREA OVERHEAD FOR FLASH MEMORY
70
Patent #:
NONE
Issue Dt:
Application #:
11935544
Filing Dt:
11/06/2007
Publication #:
Pub Dt:
05/07/2009
Title:
PROCESS OF FORMING AN ELECTRONIC DEVICE INCLUDING DEPOSITING A CONDUCTIVE LAYER OVER A SEED LAYER
71
Patent #:
Issue Dt:
10/05/2010
Application #:
11935717
Filing Dt:
11/06/2007
Publication #:
Pub Dt:
05/07/2009
Title:
CONTROLLED BIT LINE DISCHARGE FOR CHANNEL ERASES IN NONVOLATILE MEMORY
72
Patent #:
Issue Dt:
03/16/2010
Application #:
11942526
Filing Dt:
11/19/2007
Publication #:
Pub Dt:
05/21/2009
Title:
HIGH RELIABLE AND LOW POWER STATIC RANDOM ACCESS MEMORY
73
Patent #:
Issue Dt:
04/15/2014
Application #:
11943544
Filing Dt:
11/20/2007
Publication #:
Pub Dt:
05/21/2009
Title:
MEMORY BUFFERING SYSTEM THAT IMPROVES READ/WRITE PERFORMANCE AND PROVIDES LOW LATENCY FOR MOBILE SYSTEMS
74
Patent #:
Issue Dt:
07/12/2011
Application #:
11945292
Filing Dt:
11/27/2007
Publication #:
Pub Dt:
05/28/2009
Title:
SPI BANK ADDRESSING SCHEME FOR MEMORY DENSITIES ABOVE 128MB
75
Patent #:
Issue Dt:
07/19/2011
Application #:
11945316
Filing Dt:
11/27/2007
Publication #:
Pub Dt:
05/28/2009
Title:
SPI AUTO-BOOT MODE
76
Patent #:
Issue Dt:
11/25/2014
Application #:
11945534
Filing Dt:
11/27/2007
Publication #:
Pub Dt:
05/28/2009
Title:
MULTI-BUS ARCHITECTURE FOR MASS STORAGE SYSTEM-ON-CHIP CONTROLLERS
77
Patent #:
Issue Dt:
05/17/2011
Application #:
11945785
Filing Dt:
11/27/2007
Publication #:
Pub Dt:
05/28/2009
Title:
ROOM TEMPERATURE DRIFT SUPPRESSION VIA SOFT PROGRAM AFTER ERASE
78
Patent #:
Issue Dt:
11/30/2010
Application #:
11947424
Filing Dt:
11/29/2007
Publication #:
Pub Dt:
06/04/2009
Title:
WEAVABLE FIBER PHOTOVOLTAIC COLLECTORS
79
Patent #:
Issue Dt:
07/10/2012
Application #:
11949521
Filing Dt:
12/03/2007
Publication #:
Pub Dt:
06/04/2009
Title:
DIRECT INTERCONNECTION BETWEEN PROCESSOR AND MEMORY COMPONENT
80
Patent #:
Issue Dt:
01/27/2009
Application #:
11949637
Filing Dt:
12/03/2007
Title:
FORMING METAL-SEMICONDUCTOR FILMS HAVING DIFFERENT THICKNESSES WITHIN DIFFERENT REGIONS OF AN ELECTRONIC DEVICE
81
Patent #:
Issue Dt:
08/07/2012
Application #:
11950006
Filing Dt:
12/04/2007
Publication #:
Pub Dt:
06/04/2009
Title:
DATA TRANSMISSION SYSTEM-ON-CHIP MEMORY MODEL BASED VALIDATION
82
Patent #:
Issue Dt:
10/13/2015
Application #:
11950339
Filing Dt:
12/04/2007
Publication #:
Pub Dt:
06/04/2009
Title:
Method of operating a processing chamber used in forming electronic devices
83
Patent #:
Issue Dt:
11/03/2009
Application #:
11950811
Filing Dt:
12/05/2007
Publication #:
Pub Dt:
06/05/2008
Title:
METHOD AND APPARATUS FOR HIGH VOLTAGE OPERATION FOR A HIGH PERFORMANCE SEMICONDUCTOR MEMORY DEVICE
84
Patent #:
Issue Dt:
05/24/2011
Application #:
11951262
Filing Dt:
12/05/2007
Publication #:
Pub Dt:
06/11/2009
Title:
CIRCUIT PRE-CHARGE TO SENSE A MEMORY LINE
85
Patent #:
Issue Dt:
12/15/2009
Application #:
11951263
Filing Dt:
12/05/2007
Publication #:
Pub Dt:
06/11/2009
Title:
FLEXIBLE WORD LINE BOOSTING ACROSS VCC SUPPLY
86
Patent #:
Issue Dt:
07/12/2011
Application #:
11953501
Filing Dt:
12/10/2007
Publication #:
Pub Dt:
06/11/2009
Title:
MEMORY ARRAY SEARCH ENGINE
87
Patent #:
Issue Dt:
06/29/2010
Application #:
11953689
Filing Dt:
12/10/2007
Publication #:
Pub Dt:
06/11/2009
Title:
SELECTIVE APPLICATION OF WORD LINE BIAS TO MINIMIZE FRINGE EFFECTS IN ELECTROMAGNETIC FIELDS DURING ERASE OF NONVOLATILE MEMORY
88
Patent #:
Issue Dt:
02/09/2010
Application #:
11953690
Filing Dt:
12/10/2007
Publication #:
Pub Dt:
06/11/2009
Title:
WORK FUNCTION ENGINEERING FOR FN ERASE OF A MEMORY DEVICE WITH MULTIPLE CHARGE STORAGE ELEMENTS IN AN UNDERCUT REGION
89
Patent #:
Issue Dt:
07/14/2009
Application #:
11955802
Filing Dt:
12/13/2007
Publication #:
Pub Dt:
06/18/2009
Title:
REFERENCE-FREE SAMPLED SENSING
90
Patent #:
Issue Dt:
07/20/2010
Application #:
11955934
Filing Dt:
12/13/2007
Publication #:
Pub Dt:
06/18/2009
Title:
POWER SAFE TRANSLATION TABLE OPERATION IN FLASH MEMORY
91
Patent #:
Issue Dt:
06/29/2010
Application #:
11956032
Filing Dt:
12/13/2007
Publication #:
Pub Dt:
06/18/2009
Title:
PROGRAMMING IN MEMORY DEVICES USING SOURCE BITLINE VOLTAGE BIAS
92
Patent #:
Issue Dt:
11/02/2010
Application #:
11957027
Filing Dt:
12/14/2007
Publication #:
Pub Dt:
06/18/2009
Title:
CLOCK ENCODED PRE-FETCH TO ACCESS MEMORY DATA IN CLUSTERING NETWORK ENVIRONMENT
93
Patent #:
NONE
Issue Dt:
Application #:
11957028
Filing Dt:
12/14/2007
Publication #:
Pub Dt:
06/18/2009
Title:
REDUCING NOISE AND DISTURBANCE BETWEEN MEMORY STORAGE ELEMENTS USING ANGLED WORDLINES
94
Patent #:
Issue Dt:
03/20/2012
Application #:
11957226
Filing Dt:
12/14/2007
Publication #:
Pub Dt:
06/18/2009
Title:
INTELLIGENT MEMORY DATA MANAGEMENT
95
Patent #:
Issue Dt:
10/13/2009
Application #:
11957309
Filing Dt:
12/14/2007
Publication #:
Pub Dt:
06/18/2009
Title:
READING ELECTRONIC MEMORY UTILIZING RELATIONSHIPS BETWEEN CELL STATE DISTRIBUTIONS
96
Patent #:
Issue Dt:
07/07/2009
Application #:
11957366
Filing Dt:
12/14/2007
Publication #:
Pub Dt:
06/18/2009
Title:
SCAN SENSING METHOD THAT IMPROVES SENSING MARGINS
97
Patent #:
Issue Dt:
05/31/2011
Application #:
11957737
Filing Dt:
12/17/2007
Publication #:
Pub Dt:
06/18/2009
Title:
SI TRENCH BETWEEN BITLINE HDP FOR BVDSS IMPROVEMENT
98
Patent #:
Issue Dt:
10/13/2009
Application #:
11957787
Filing Dt:
12/17/2007
Publication #:
Pub Dt:
06/18/2009
Title:
HETERO-STRUCTURE VARIABLE SILICON RICH NITRIDE FOR MULTIPLE LEVEL MEMORY FLASH MEMORY DEVICE
99
Patent #:
Issue Dt:
08/30/2011
Application #:
11957793
Filing Dt:
12/17/2007
Publication #:
Pub Dt:
06/18/2009
Title:
ADAPTIVE SYSTEM BOOT ACCELERATOR FOR COMPUTING SYSTEMS
100
Patent #:
Issue Dt:
08/23/2011
Application #:
11958223
Filing Dt:
12/17/2007
Publication #:
Pub Dt:
06/18/2009
Title:
METHODS OF FORMING ELECTRONIC DEVICES BY ION IMPLANTING
Assignors
1
Exec Dt:
05/10/2010
2
Exec Dt:
05/10/2010
3
Exec Dt:
05/10/2010
4
Exec Dt:
05/10/2010
Assignee
1
745 SEVENTH AVENUE
NEW YORK, NEW YORK 10019
Correspondence name and address
LATHAM & WATKINS, C/O JULIE DALKE
650 TOWN CENTER DR, 20TH FLOOR
042243-0080
COSTA MESA, CA 92626

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