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10/26/1999
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08774307
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12/26/1996
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Title:
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09/08/1998
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08795024
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02/04/1997
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Title:
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SYSTEM FOR CONSTANT FIELD ERASURE IN A FLASH EPROM
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10/13/1998
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08799074
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02/11/1997
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Title:
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HIGH-VOLTAGE CMOS LEVEL SHIFTER
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Issue Dt:
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08/18/1998
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08799236
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Filing Dt:
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02/14/1997
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Title:
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METHOD FOR ANNEALING DAMAGED SEMICONDUCTOR REGIONS ALLOWING FOR ENHANCED OXIDE GROWTH
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12/22/1998
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08801305
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02/18/1997
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Title:
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NON-VOLATILE STORAGE DEVICE REFRESH TIME DETECTOR
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09/01/1998
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08808237
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Filing Dt:
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02/28/1997
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Title:
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HIGH VOLTAGE NMOS PASS GATE FOR INTEGRATED CIRCUIT WITH HIGH VOLTAGE GENERATOR
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Patent #:
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09/08/1998
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08810164
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Filing Dt:
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02/28/1997
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Title:
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CHANNEL HOT-CARRIER PAGE WRITE FOR NAND APPLICATIONS
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09/29/1998
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08810170
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02/28/1997
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Title:
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OPTIMIZED BIASING SCHEME FOR NAND READ AND HOT-CARRIER WRITE OPERATIONS
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08/03/1999
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08813562
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03/07/1997
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Title:
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METHOD OF SPACER FORMATION AND SOURCE PROTECTION AFTER SELF- ALIGNED SOURCE IS FORMED AND DEVICE PROVIDED BY SUCH A METHOD
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09/08/1998
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08815835
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03/12/1997
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Title:
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NON-VOLATILE MEMORY DEVICE HAVING A FLOATING GATE WITH ENHANCED CHARGE RETENTION
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01/05/1999
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08831571
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04/09/1997
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Title:
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MEMORY CELL PROGRAMMING WITH CONTROLLED CURRENT INJECTION
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Patent #:
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03/30/1999
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08837556
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04/21/1997
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Title:
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MULTILAYER FLOATING GATE FIELD EFFECT TRANSISTOR STRUCTURE FOR USE IN INTEGRATED CIRCUIT DEVICES
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08/04/1998
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08853185
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Filing Dt:
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05/09/1997
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Title:
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MULTIPLE BITS- PER- CELL FLASH EEPROM MEMORY CELLS WITH WIDE PROGRAM AND ERASE VT WINDOW
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08/18/1998
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08858589
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05/19/1997
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Title:
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MEMORY DEVICE USING A REDUCED WORD LINE VOLTAGE DURING READ OPERATIONS AND A METHOD OF ACCESSING SUCH A MEMORY DEVICE
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11/09/1999
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08870045
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06/05/1997
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Title:
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TUBE FOR FLASH MINIATURE CARD
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09/07/1999
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08878119
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Filing Dt:
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06/18/1997
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Title:
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METHOD OF FABRICATING AN EPROM TYPE DEVICE WITH REDUCED PROCESS RESIDUES
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Patent #:
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Issue Dt:
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05/19/1998
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08884547
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06/27/1997
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Title:
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A BIT LINE DISCHARGE METHOD FOR READING A MULTIPLE BITS-PER-CELL FLASH EEPROM
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08/07/2001
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08885140
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06/30/1997
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Title:
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METHOD AND APPARATUS FOR CONTROLLING THE THICKNESS OF A GATE OXIDE IN A SEMICONDUCTOR MANUFACTURING PROCESS
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Patent #:
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Issue Dt:
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10/05/1999
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08891422
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07/09/1997
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Title:
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METHOD OF MAKING A SEMICONDUCTOR DEVICE WITH ADJUSTABLE THRESHOLD VOLTAGE
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Issue Dt:
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12/01/1998
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08914543
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08/19/1997
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Title:
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HIGH VOLTAGE NMOS PASS GATE HAVING SUPPLY RANGE, AREA, AND SPEED ADVANTAGES
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08/17/1999
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08917149
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08/25/1997
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Title:
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REDUCTION OF CHARGE LOSS IN NONVOLATILE MEMORY CELLS BY PHOSPHORUS IMPLANTATION INTO PECVD NITRIDE/OXYNITRIDE FILMS
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Issue Dt:
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03/16/1999
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08938048
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09/26/1997
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Title:
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MEMORY BLOCK SELECT USING MULTIPLE WORD LINES TO ADDRESS A SINGLE MEMORY CELL ROW
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Issue Dt:
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03/16/1999
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08938292
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Filing Dt:
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09/26/1997
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Title:
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SELECTIVE BIT LINE RECOVERY IN A MEMORY ARRAY
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Issue Dt:
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06/15/1999
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08940674
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Filing Dt:
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09/30/1997
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Title:
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A DUAL SOURCE SIDE POLYSILICON SELECT GATE STRUCTURE UTILIZING SINGLE TUNNEL OXIDE FOR NAND ARRAY FLASH MEMORY
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Patent #:
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Issue Dt:
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03/30/1999
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Application #:
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08947123
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Filing Dt:
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10/08/1997
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Title:
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MEMORY CELL FOR STORING AT LEAST THREE LOGIC STATES
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Patent #:
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Issue Dt:
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03/30/1999
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Application #:
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08955794
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Filing Dt:
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10/22/1997
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Title:
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MEMORY CELL FABRICATION EMPLOYING AN INTERPOLY GATE DIELECTRIC ARRANGED UPON A POLISHED FLOATING GATE
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Patent #:
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Issue Dt:
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11/23/2004
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08974971
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Filing Dt:
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11/20/1997
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Title:
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NON-VOLATILE MEMORY SYSTEM HAVING A PROGRAMMABLY SELECTABLE BOOT CODE SECTION SIZE
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Issue Dt:
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12/07/1999
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Application #:
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08976303
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Filing Dt:
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11/21/1997
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Title:
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BIOS MEMORY AND MULTIMEDIA DATA STORAGE COMBINATION
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Patent #:
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Issue Dt:
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02/01/2000
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Application #:
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08978107
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Filing Dt:
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11/25/1997
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Title:
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METHOD OF FABRICATING A HIGH DIELECTRIC CONSTANT INTERPOLYSILICON DIELECTRIC STRUCTURE FOR A LOW VOLTAGE NON-VOLATILE MEMORY
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Patent #:
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Issue Dt:
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02/15/2000
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08978398
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Filing Dt:
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11/25/1997
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Title:
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METHOD OF FABRICATING AN OXYNITRIDE-CAPPED HIGH DIELECTRIC CONSTANT INTERPOLYSILICON DIELECTRIC STRUCTURE FOR A LOW VOLTAGE NON-VOLATILE MEMORY.
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Issue Dt:
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01/25/2000
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08982186
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Filing Dt:
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12/17/1997
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Title:
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METHOD FOR FORMING A LOW BARRIER HEIGHT OXIDE LAYER ON A SILICON SUBSTRATE
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Patent #:
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Issue Dt:
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11/09/1999
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Application #:
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08986160
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Filing Dt:
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12/05/1997
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Title:
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SIDEWALL SPACER FOR PROTECTING TUNNEL OXIDE DURING ISOLATION TRENCH FORMATION IN SELF-ALIGNED FLASH MEMORY CORE
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Issue Dt:
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12/14/1999
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08986860
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Filing Dt:
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12/08/1997
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Title:
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METHOD OF ELIMINATING POLY STRINGER IN A MEMORY DEVICE
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Issue Dt:
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04/04/2000
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Application #:
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08986951
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Filing Dt:
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12/08/1997
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Title:
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ELIMINATION OF POLY STRINGERS WITH STRAIGHT POLY PROFILE
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Patent #:
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Issue Dt:
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08/03/1999
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Application #:
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08986953
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Filing Dt:
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12/08/1997
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Title:
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REDUCTION OF ONO FENCE DURING SELF-ALIGNED ETCH TO ELIMINATE POLY STRINGERS
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Issue Dt:
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12/14/1999
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Application #:
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08989820
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Filing Dt:
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12/12/1997
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Title:
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SEMICONDUCTOR ISOLATION PROCESS TO MINIMIZE WEAK OXIDE PROBLEMS
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Issue Dt:
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11/30/1999
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Application #:
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08991052
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Filing Dt:
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12/16/1997
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Title:
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SEMICONDUCTOR DEVICE WITH MULTIPLE CONTACT SIZES
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Issue Dt:
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06/06/2000
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Application #:
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08991299
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Filing Dt:
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12/16/1997
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Title:
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INTERLEVEL DIELECTRIC THICKNESS MONITOR FOR COMPLEX SEMICONDUCTOR CHIPS
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Issue Dt:
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04/29/2003
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08991448
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Filing Dt:
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12/16/1997
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Title:
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FLASH MEMORY GATE COUPLING USING HSG POLYSILICON
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Issue Dt:
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01/12/1999
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Application #:
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08991466
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Filing Dt:
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12/16/1997
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Title:
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PROGRAMMING OF MEMORY CELLS USING CONNECTED FLOATING GATE ANALOG REFERENCE CELL
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Issue Dt:
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10/03/2000
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08991687
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12/16/1997
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Title:
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NON-SELF-ALIGNED SIDE CHANNEL IMPLANTS FOR FLASH MEMORY CELLS
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05/25/1999
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08992077
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12/17/1997
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Title:
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METHOD TO IMPROVE TESTING SPEED OF MEMORY
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Issue Dt:
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02/22/2000
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08992536
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Filing Dt:
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12/17/1997
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Title:
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METHOD FOR FULLY PLANARIZED CONDUCTIVE LINE FOR A STACK GATE
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Issue Dt:
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05/14/2002
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08992616
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12/17/1997
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Title:
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METHOD AND SYSTEM FOR PROVIDING LOCALIZED GATE EDGE ROUNDING WITH MINIMAL ENCROACHMENT AND GATE EDGE LIFTING
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Issue Dt:
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08/15/2000
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08992618
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Filing Dt:
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12/17/1997
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Title:
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METHOD AND SYSTEM FOR PROVIDING A DRAIN SIDE POCKET IMPLANT
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Issue Dt:
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09/07/1999
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Application #:
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08992622
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Filing Dt:
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12/17/1997
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Title:
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METHOD AND SYSTEM FOR SELECTED SOURCE DURING READ AND PROGRAMMING OF FLASH MEMORY
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Issue Dt:
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03/07/2000
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Application #:
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08992950
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Filing Dt:
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12/18/1997
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Title:
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METHODS AND ARRANGEMENTS FOR FORMING A FLOATING GATE IN NON-VOLATILE MEMORY SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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10/26/1999
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Application #:
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08992951
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Filing Dt:
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12/18/1997
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Title:
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METHODS AND ARRANGEMENTS FOR FORMING A TAPERED FLOATING GATE IN NON-VOLATILE MEMORY SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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07/10/2001
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Application #:
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08992960
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Filing Dt:
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12/18/1997
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Title:
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METHODS AND ARRANGEMENTS FOR IMPROVED FORMATION OF CONTROL AND FLOATING GATES IN NON-VOLATILE MEMORY SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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09/26/2000
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Application #:
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08992961
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Filing Dt:
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12/18/1997
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Title:
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NON-VOLATILE TRENCH SEMICONDUCTOR DEVICE HAVING A SHALLOW DRAIN REGION
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Issue Dt:
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02/06/2001
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Application #:
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08993062
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Filing Dt:
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12/18/1997
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Title:
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DEVICE INITIALIZING SYSTEM WITH PROGRAMMABLE ARRAY LOGIC CONFIGURED TO CAUSE NON-VOLATILE MEMORY TO OUTPUT ADDRESS AND DATA INFORMATION TO THE DEVICE IN A PRESCRIBED SEQUENCE
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Issue Dt:
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05/08/2001
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Application #:
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08993149
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12/18/1997
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Title:
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METHODOLOGY FOR ACHIEVING DUAL FIELD OXIDE THICKNESSES
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Patent #:
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Issue Dt:
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11/30/1999
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Application #:
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08993343
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Filing Dt:
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12/18/1997
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Title:
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MANUFACTURING PROCESS TO ELIMINATE POLYSTRINGERS IN HIGH DENSITY NAND-TYPE FLASH MEMORY DEVICES
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Patent #:
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Issue Dt:
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08/28/2001
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08993344
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Filing Dt:
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12/18/1997
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Title:
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MANUFACTURING PROCESS TO ELIMINATE ONO FENCE MATERIAL IN HIGH DENSITY NAND-TYPE FLASH MEMORY DEVICES
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Issue Dt:
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12/23/2003
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08993368
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12/18/1997
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Title:
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NOVEL NAND TYPE CORE CELL STRUCTURE FOR A HIGH DENSITY FLASH MEMORY DEVICE HAVING A UNIQUE SELECT GATE TRANSISTOR CONFIGURATION
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Issue Dt:
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05/16/2000
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08993409
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Filing Dt:
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12/18/1997
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Title:
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METHODS FOR FORMING A CONTROL GATE APPARATUS IN NON-VOLATILE MEMORY SEMICONDUCTOR DEVICES
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Issue Dt:
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09/05/2000
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Application #:
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08993443
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Filing Dt:
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12/18/1997
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Title:
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NITROGEN ION IMPLANTED AMORPHOUS SILICON TO PRODUCE OXIDATION RESISTANT AND FINER GRAIN POLYSILICON BASED FLOATING GATES
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Patent #:
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Issue Dt:
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10/31/2000
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Application #:
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08993444
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Filing Dt:
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12/18/1997
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Title:
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IN SITU P DOPED AMORPHOUS SILICON BY NH3 TO FORM OXIDATION RESISTANT AND FINER GRAIN FLOATING GATES.
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Issue Dt:
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08/17/1999
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08993599
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Filing Dt:
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12/18/1997
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Title:
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METHOD AND SYSTEM FOR SOURCE ONLY REOXIDATION AFTER JUNCTION IMPLANT FOR FLASH MEMORY DEVICES
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Issue Dt:
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02/15/2000
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Application #:
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08993600
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Filing Dt:
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12/18/1997
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Title:
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METHOD AND SYSTEM FOR USING A SPACER TO OFFSET IMPLANT DAMAGE AND REDUCE LATERAL DIFFUSION IN FLASH MEMORY DEVICES
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Issue Dt:
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12/21/1999
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Application #:
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08993634
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Filing Dt:
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12/18/1997
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Title:
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SPLIT VOLTAGE FOR NAND FLASH
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Issue Dt:
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06/27/2000
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08993716
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Filing Dt:
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12/18/1997
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Title:
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METHODOLOGY FOR ACHIEVING DUAL GATE OXIDE THICKNESSES
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Patent #:
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Issue Dt:
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01/18/2000
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Application #:
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08993787
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Filing Dt:
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12/19/1997
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Title:
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METHOD AND SYSTEM FOR GATE STACK REOXIDATION CONTROL
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Patent #:
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Issue Dt:
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12/14/1999
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Application #:
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08993890
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Filing Dt:
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12/18/1997
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Title:
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NON- VOLATILE TRENCH SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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12/11/2001
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Application #:
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08994140
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Filing Dt:
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12/19/1997
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Title:
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METHOD FOR LATERALLY PEAKED SOURCE DOPING PROFILES FOR BETTER ERASE CONTROL IN FLASH MEMORY DEVICES
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Patent #:
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Issue Dt:
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12/26/2000
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Application #:
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09000739
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Filing Dt:
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12/30/1997
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Title:
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A LOW DIELECTRIC CONSTANT MATERIAL AND METHOD OF APPLICATION TO ISOLATE CONDUCTIVE LINES
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Patent #:
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Issue Dt:
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10/26/1999
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Application #:
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09002783
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01/05/1998
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Title:
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METHOD FOR PREVENTING P1 PUNCHTHROUGH
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Patent #:
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Issue Dt:
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05/22/2001
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Application #:
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09006495
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Filing Dt:
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01/13/1998
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Title:
|
TRUNGSTEN PLUG FORMATION
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Patent #:
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Issue Dt:
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02/13/2001
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Application #:
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09006757
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Filing Dt:
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01/14/1998
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Title:
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FLASH EPROM CELL WITH REDUCED SHORT CHANNEL EFFECT AND METHOD FOR PROVIDING SAME
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Patent #:
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Issue Dt:
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12/10/2002
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Application #:
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09008162
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Filing Dt:
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01/16/1998
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Title:
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FLASH MEMORY ARRAY WITH DUAL FUNCTION CONTROL LINES AND ASYMMETRICAL SOURCE AND DRAIN JUNCTIONS
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Patent #:
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Issue Dt:
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12/14/1999
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Application #:
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09008415
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Filing Dt:
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01/16/1998
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Title:
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PROCESS FOR FABRICATING A FLASH MEMORY WITH DUAL FUNCTION CONTROL LINES
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Patent #:
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Issue Dt:
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10/26/2004
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Application #:
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09019409
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Filing Dt:
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02/05/1998
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Title:
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METHOD FOR FORMING ISOLATION IN FLASH MEMORY WAFER
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Patent #:
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Issue Dt:
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03/30/1999
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Application #:
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09023241
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Filing Dt:
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02/13/1998
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Title:
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NON-UNIFORM THRESHOLD VOLTAGE ADJUSTMENT IN FLASH EPROMS THROUGH GATE WORK FUNCTION ALTERATION
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Patent #:
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Issue Dt:
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10/24/2000
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Application #:
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09023497
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Filing Dt:
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02/13/1998
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Title:
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FLOATING GATE CAPACITOR FOR USE IN VOLTAGE REGULATORS
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Patent #:
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Issue Dt:
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07/13/1999
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Application #:
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09026358
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Filing Dt:
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02/19/1998
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Title:
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DOUBLE DENSITY V NONVOLATILE MEMORY CELL
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Patent #:
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Issue Dt:
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08/08/2000
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Application #:
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09032362
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Filing Dt:
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02/27/1998
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Title:
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MULTIPLE CHIP HYBRID PACKAGE USING BUMP TECHNOLOGY
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Patent #:
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Issue Dt:
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07/18/2000
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Application #:
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09032398
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Filing Dt:
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02/27/1998
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Title:
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MULTI-CHIP PACKAGING USING BUMP TECHNOLOGY
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Patent #:
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Issue Dt:
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02/13/2001
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Application #:
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09033642
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Filing Dt:
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03/03/1998
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Title:
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METHOD AND APPARATUS FOR CONTROLLING THE THICKNESS OF A GATE OXIDE IN A SEMICONDUCTOR MANUFACTURING PROCESS
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Patent #:
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Issue Dt:
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03/28/2000
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Application #:
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09033723
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Filing Dt:
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03/03/1998
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Title:
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ELIMINATION OF OXYNITRIDE (ONO) ETCH RESIDUE AND POLYSILICON STRINGERS THROUGH ISOLATION OF FLOATING GATES ON ADJACENT BITLINES BY POLYSILICON OXIDATION
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Patent #:
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Issue Dt:
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08/29/2000
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Application #:
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09033836
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Filing Dt:
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03/03/1998
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Title:
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ELIMINATION OF OXYNITRIDE (ONO) ETCH RESIDUE AND POLYSILICON STRI NGERS THROUGH ISOLATION OF FLOATING GATES ON ADJACENT BITLINES BY POLYSILICON OXIDATION
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Patent #:
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Issue Dt:
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02/29/2000
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Application #:
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09033916
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Filing Dt:
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03/03/1998
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Title:
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ELIMINATION OF OXYNITRIDE (ONO) ETCH RESIDUE AND POLYSILICON STRINGERS THROUGH ISOLATION OF FLOATING GATES ON ADJACENT BITLINES BY POLYSILICON OXIDATION
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Patent #:
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Issue Dt:
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11/14/2000
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Application #:
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09039783
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Filing Dt:
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03/16/1998
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Title:
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LARGE ANGLE IMPLANTATION TO PREVENT FIELD TURN-ON UNDER SELECT GATE TRANSISTOR FIELD OXIDE REGION FOR NON-VOLATILE MEMORY DEVICES
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Patent #:
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Issue Dt:
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11/28/2000
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Application #:
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09040107
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Filing Dt:
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03/17/1998
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Title:
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NEW APPROACH FOR THE FORMATION OF SEMICONDUCTOR DEVICES WHICH REDUCES BAND-TO-BAND TUNNELING CURRENT AND SHORT-CHANNEL EFFECTS
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Patent #:
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Issue Dt:
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06/19/2001
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Application #:
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09040823
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Filing Dt:
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03/18/1998
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Title:
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PROCESS FOR FABRICATING A FLASH MEMORY DEVICE
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Patent #:
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Issue Dt:
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06/19/2001
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Application #:
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09044389
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Filing Dt:
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03/18/1998
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Title:
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STEPPER ALIGNMENT MARK FORMATION WITH DUAL FIELD OXIDE PROCESS
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Patent #:
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Issue Dt:
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11/09/1999
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Application #:
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09045013
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Filing Dt:
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03/20/1998
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Title:
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NARROWER ERASE DISTRIBUTION FOR FLASH MEMORY BY SMALLER POLY GRAIN SIZE
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Patent #:
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Issue Dt:
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07/17/2001
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Application #:
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09047237
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Filing Dt:
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03/25/1998
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Title:
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CAPACITOR FOR USE IN A CAPACITOR DIVIDER THAT HAS A FLOATING GATE TRANSISTOR AS A CORRESPONDING CAPACITOR
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Patent #:
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Issue Dt:
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09/04/2001
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Application #:
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09052057
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Filing Dt:
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03/30/1998
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Title:
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TRENCHED GATE NON-VOLATILE SEMICONDUCTOR DEVICE WITH THE SOURCE/DRAIN REGIONS SPACED FROM THE TRENCH BY SIDEWALL DOPINGS
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Patent #:
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Issue Dt:
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05/01/2001
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Application #:
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09052058
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Filing Dt:
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03/30/1998
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Title:
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TRENCHED GATE SEMICONDUCTOR DEVICE AND METHOD FOR LOW POWER APPLICATIONS
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Patent #:
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Issue Dt:
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11/14/2000
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Application #:
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09052060
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Filing Dt:
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03/30/1998
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Title:
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FULLY RECESSED SEMICONDUCTOR DEVICE AND METHOD FOR LOW POWER APPLICATIONS WITH SINGLE WRAP AROUND BURIED DRAIN REGION
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Patent #:
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Issue Dt:
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11/14/2000
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Application #:
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09052061
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Filing Dt:
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03/30/1998
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Title:
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FULLY RECESSED SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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11/23/1999
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Application #:
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09052062
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Filing Dt:
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03/30/1998
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Title:
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TRENCHED GATE NON-VOLATILE SEMICONDUCTOR DEVICE AND METHOD WITH CORNER DOPING AND SIDEWALL DOPING
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Patent #:
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Issue Dt:
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05/02/2000
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Application #:
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09061515
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Filing Dt:
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04/16/1998
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Title:
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ELIMINATION OF POLY CAP FOR EASY POLY1 CONTACT FOR NAND PRODUCT
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Patent #:
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Issue Dt:
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12/07/1999
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Application #:
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09063688
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Filing Dt:
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04/21/1998
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Title:
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DUAL SOURCE SIDE POLYSILICON SELECT GATE STRUCTURE AND PROGRAMMING METHOD UTILIZING SINGLE TUNNEL OXIDE FOR NAND ARRAY FLASH MEMORY
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Patent #:
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Issue Dt:
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04/03/2001
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Application #:
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09076584
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Filing Dt:
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05/12/1998
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Title:
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METHODS AND ARRANGEMENTS FOR REDUCING STRESS AND PREVENTING CRACKING IN A SILICIDE LAYER
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Patent #:
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Issue Dt:
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12/12/2000
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Application #:
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09076662
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Filing Dt:
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05/12/1998
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Title:
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METHODS FOR REMOVING SILICIDE RESIDUE IN A SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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06/13/2000
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Application #:
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09076663
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Filing Dt:
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05/12/1998
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Title:
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METHODS FOR PREVENTING SILICIDE RESIDUE FORMATION IN A SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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05/15/2001
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Application #:
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09082607
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Filing Dt:
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05/20/1998
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Title:
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SHALLOW TRENCH ISOLATION FILLED WITH THERMAL OXIDE
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Patent #:
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Issue Dt:
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05/04/1999
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Application #:
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09085552
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Filing Dt:
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05/27/1998
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Title:
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METHOD FOR ERASING FLASH ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY (EEPROM )
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Patent #:
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Issue Dt:
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12/05/2000
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Application #:
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09085680
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Filing Dt:
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05/27/1998
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Title:
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METHOD FOR ERASING FLASH ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY(EEPROM)
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