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02/23/1999
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05/27/1998
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03/07/2000
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06/05/1998
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09/07/1999
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06/08/1998
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05/16/2000
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06/16/1998
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11/21/2000
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06/17/1998
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07/27/1999
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06/23/1998
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10/26/1999
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06/23/1998
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04/09/2002
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06/29/1998
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07/18/2000
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07/01/1998
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12/12/2000
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07/02/1998
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02/12/2002
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07/02/1998
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09/12/2000
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07/07/1998
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12/12/2000
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07/17/1998
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11/02/1999
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07/17/1998
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08/29/2000
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07/17/1998
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01/16/2001
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07/21/1998
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06/01/1999
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08/03/1998
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08/08/2000
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08/03/1998
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07/09/2002
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08/04/1998
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09/13/2001
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01/04/2000
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08/12/1998
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04/18/2000
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08/12/1998
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08/08/2000
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08/14/1998
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08/22/2000
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08/14/1998
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10/26/1999
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08/28/1998
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09/26/2000
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08/31/1998
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SCALABLE AND RELIABLE INTEGRATED CIRCUIT INTER-LEVEL DIELECTRIC
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10/17/2000
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08/31/1998
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11/14/2000
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09/02/1998
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05/09/2000
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09/16/1998
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01/04/2000
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09/16/1998
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12/14/1999
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09154074
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09/16/1998
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03/07/2000
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09/23/1998
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12/21/1999
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09/23/1998
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08/14/2001
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09/23/1998
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01/14/2003
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09/25/1998
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09/06/2001
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11/23/1999
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09/24/1998
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06/05/2001
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09/30/1998
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06/26/2001
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09/30/1998
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03/20/2001
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10/05/1998
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METHOD FOR ERASING FLASH ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY (EEPROM)
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10/17/2000
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10/05/1998
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12/19/2000
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10/13/1998
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04/11/2000
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10/14/1998
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FLASH MEMORY DEVICE HAVING HIGH PERMITTIVITY STACKED DIELECTRIC AND FABRICATION THEREOF
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11/30/1999
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10/20/1998
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SCHEME FOR PAGE ERASE AND ERASE VERIFY IN A NON -VOLATILE MEMORY ARRAY
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11/02/1999
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10/20/1998
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04/03/2001
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10/22/1998
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01/23/2001
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10/23/1998
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04/09/2002
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10/30/1998
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HIGH VOLTAGE TRANSISTOR WITH LOW BODY EFFECT AND LOW LEAKAGE
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11/12/2002
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10/31/1998
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PSEUDO-CONCURRENCY BETWEEN A VOLATILE MEMORY AND A NON-VOLATILE MEMORY ON A SAME DATA BUS
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06/13/2000
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11/11/1998
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LPCVD OXIDE AND RTA FOR TOP OXIDE OF ONO FILM TO IMPROVE RELIABILITY FOR FLASH MEMORY DEVICES
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04/17/2001
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11/24/1998
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METHOD FOR FABRICATING A HIGH-DENSITY AND HIGH-RELIABILITY EEPROM DEVICE
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06/27/2000
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11/25/1998
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05/29/2001
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11/25/1998
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04/30/2002
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12/04/1998
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METHOD OF FORMING ONO STACKED FILMS AND DCS TUNGSTEN SILICIDE GATE TO IMPROVE POLYCIDE GATE PERFORMANCE FOR FLASH MEMORY DEVICES
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06/27/2000
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01/14/1999
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EEPROM DECODER BLOCK HAVING A P-WELL COUPLED TO A CHARGE PUMP FOR CHARGING THE P-WELL AND METHOD OF PROGRAMMING WITH THE EEPROM DECODER BLOCK
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02/04/2003
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02/04/1999
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SEMICONDUCTOR DEVICES WITH REDUCED CONTROL GATE DIMENSIONS
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06/12/2001
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02/18/1999
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LOW DIELECTRIC SEMICONDUCTOR DEVICE WITH RIGID, CONDUCTIVELY LINED INTERCONNECTION SYSTEM
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12/23/2003
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02/18/1999
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LOW DIELECTRIC METAL SILICIDE LINED INTERCONNECTION SYSTEM
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06/12/2001
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09/08/1998
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NOVEL PROCESS FOR RELIABLE ULTRATHIN OXYNITRIDE FORMATION
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01/08/2002
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02/22/1999
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IN LINE YIELD PREDICTION USING ADC DETERMINED KILL RATIOS DIE HEALTH STATISTICS AND DIE STACKING
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04/24/2001
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02/25/1999
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03/12/2002
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03/05/1999
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EFFECT OF DOPED AMORPHOUS SI THICKNESS ON BETTER POLY 1 CONTACT RESISTANCE PERFORMANCE FOR NAND TYPE FLASH MEMORY DEVICES
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02/06/2001
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03/05/1999
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METHOD TO ELIMATE SILICIDE CRACKING FOR NAND TYPE FLASH MEMORY DEVICES BY IMPLANTING A POLISH RATE IMPROVER INTO THE SECOND POLYSILICON LAYER AND POLISHING IT
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10/30/2001
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03/05/1999
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11/29/2001
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METHOD OF FORMING HIGH K TANTALUM PENTOXIDE TA205 INSTEAD OF ONO STACKED FILMS TO INCREASE COUPLING RATIO AND IMPROVE RELIABILITY FOR FLASH MEMORY DEVICES
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12/19/2000
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03/11/1999
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AMMONIA ANNEALED AND WET OXIDIZED LPCVD OXIDE TO REPLACE ONO FILMS FOR HIGH INTEGRATED FLASH MEMORY DEVICES
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05/23/2000
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03/18/1999
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09/25/2001
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03/19/1999
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SHARED MEMORY APPARATUS AND METHOD FOR MULTIPROCESSOR SYSTEMS
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11/07/2000
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03/31/1999
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Title:
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BARRIER LAYER DECREASES NITROGEN CONTAMINATION OF PERIPHERAL GATE REGIONS DURING TUNNEL OXIDE NITRIDATION
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Patent #:
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Issue Dt:
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04/16/2002
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Application #:
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09286464
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Filing Dt:
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04/06/1999
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Title:
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METHOD FOR TRIMMING A PHOTORESIST PATTERN LINE FOR MEMORY GATE ETCHING
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Patent #:
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Issue Dt:
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02/13/2001
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Application #:
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09307259
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Filing Dt:
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05/06/1999
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Title:
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RAMPED OR STEPPED GATE CHANNEL ERASE FOR FLASH MEMORY APPLICATION
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Patent #:
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Issue Dt:
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11/12/2002
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Application #:
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09307312
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Filing Dt:
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05/07/1999
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Publication #:
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Pub Dt:
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02/07/2002
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Title:
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METHOD AND APPARATUS FOR A SEMICONDUCTOR DEVICE WITH ADJUSTABLE THRESHOLD VOLTAGE
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Patent #:
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Issue Dt:
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05/08/2001
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Application #:
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09309994
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Filing Dt:
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05/11/1999
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Title:
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CORE FIELD ISOLATION FOR A NAND FLASH MEMORY
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Patent #:
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Issue Dt:
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06/24/2003
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Application #:
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09314574
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Filing Dt:
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05/18/1999
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Title:
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DATA PRE-READING AND ERROR CORRECTION CIRCUIT FOR A MEMORY DEVICE
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Patent #:
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Issue Dt:
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08/20/2002
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Application #:
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09314575
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Filing Dt:
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05/18/1999
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Title:
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METHOD OF DUAL USE OF NON-VOLATILE MEMORY FOR ERROR CORRECTION
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Patent #:
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Issue Dt:
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04/30/2002
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Application #:
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09322195
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Filing Dt:
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05/28/1999
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Title:
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METHOD OF UTILIZING FAST CHIP ERASE TO SCREEN ENDURANCE REJECTS
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Patent #:
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Issue Dt:
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03/28/2000
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Application #:
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09334393
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Filing Dt:
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06/16/1999
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Title:
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THREE-DIMENSIONAL NON-VOLATILE MEMORY
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Patent #:
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Issue Dt:
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12/12/2000
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Application #:
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09336057
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Filing Dt:
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06/18/1999
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Title:
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METHOD OF SPACER FORMATION AND SOURCE PROTECTION AFTER SELF-ALIGNED SOURCE FORMED AND A DEVICE PROVIDED BY SUCH A METHOD
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Patent #:
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Issue Dt:
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05/15/2001
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Application #:
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09348583
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Filing Dt:
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07/07/1999
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Title:
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LIGHT FLOATING GATE DOPING TO IMPROVE TUNNEL OXIDE RELIABILITY
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Patent #:
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Issue Dt:
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03/20/2001
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Application #:
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09349603
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Filing Dt:
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07/09/1999
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Title:
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METHOD OF FORMING SELECT GATE TO IMPROVE RELIABILITY AND PERFORMANCE FOR NAND TYPE FLASH MEMORY DEVICES
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Patent #:
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Issue Dt:
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05/22/2001
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Application #:
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09352801
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Filing Dt:
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07/13/1999
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Title:
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THIN FLOATING GATE AND CONDUCTIVE SELECT GATE IN SITU DOPED AMORPHOUS SILICON MATERIAL FOR NAND TYPE FLASH MEMORY DEVICE APPLICATIONS
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Patent #:
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Issue Dt:
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05/29/2001
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Application #:
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09353267
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Filing Dt:
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07/14/1999
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Title:
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REDUCTION OF VOLTAGE STRESS ACROSS A GATE OXIDE AND ACROSS A JUNCTION WITHIN A HIGH VOLTAGE TRANSISTOR OF AN ERASABLE MEMORY DEVICE
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Patent #:
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Issue Dt:
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04/03/2001
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Application #:
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09353781
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Filing Dt:
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07/15/1999
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Title:
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SEMICONDUCTOR DEVICE WITH MULTIPLE CONTACT SIZES
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Patent #:
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Issue Dt:
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08/13/2002
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Application #:
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09357333
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Filing Dt:
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07/20/1999
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Title:
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METHODS AND ARRANGEMENTS FOR FORMING A SINGLE INTERPOLY DIELECTRIC LAYER IN A SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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07/31/2001
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Application #:
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09364982
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Filing Dt:
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07/31/1999
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Title:
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METHOD FOR INHIBITING TUNNEL OXIDE GROWTH AT THE EDGES OF A FLOATING GATE DURING SEMICONDUCOR DEVICE PROCESSING
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Patent #:
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Issue Dt:
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03/04/2003
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Application #:
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09366369
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Filing Dt:
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08/03/1999
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Title:
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DEVICE MODELING AND CHARACTERIZATION STRUCTURE WITH MULTIPLEXED PADS
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Patent #:
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Issue Dt:
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10/09/2001
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Application #:
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09368073
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Filing Dt:
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08/03/1999
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Title:
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METHOD FOR REDUCED GATE ASPECT RATIO TO IMPROVE GAP-FILL AFTER SPACER ETCH
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Patent #:
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Issue Dt:
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11/27/2001
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Application #:
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09368247
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Filing Dt:
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08/03/1999
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Title:
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METHOD FOR MONITORING SECOND GATE OVER-ETCH IN A SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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02/13/2001
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Application #:
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09369600
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Filing Dt:
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08/06/1999
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Title:
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MULTI STATE SENSING OF NAND MEMORY CELLS BY VARYING SOURCE BIAS
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|
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Patent #:
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Issue Dt:
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04/17/2001
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Application #:
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09369638
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Filing Dt:
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08/06/1999
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Title:
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METHOD FOR PROVIDING A DOPANT LEVEL FOR POLYSILICON FOR FLASH MEMORY DEVICES
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Patent #:
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Issue Dt:
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12/26/2000
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Application #:
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09370010
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Filing Dt:
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08/06/1999
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Title:
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MULTI STATE SENSING OF NAND MEMORY CELLS BY APPLYING REVERSE-BIAS VOLTAGE
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|
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Patent #:
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Issue Dt:
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01/09/2001
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Application #:
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09370380
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Filing Dt:
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08/09/1999
|
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Title:
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RAMPED GATE TECHNIQUE FOR SOFT PROGRAMMING TO TIGHTEN THE VT DISTRIBUTION
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|
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Patent #:
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Issue Dt:
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06/17/2003
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Application #:
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09372406
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Filing Dt:
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08/10/1999
|
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Title:
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METHOD OF REDUCING PROGRAM DISTURBS IN NAND TYPE FLASH MEMORY DEVICES
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|
|
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Patent #:
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|
Issue Dt:
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11/28/2000
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Application #:
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09374059
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Filing Dt:
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08/12/1999
|
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Title:
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FLOATING GATE ENGINEERING TO IMPROVE TUNNEL OXIDE RELIABILITY FOR FLASH MEMORY DEVICES
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|
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Patent #:
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|
Issue Dt:
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05/07/2002
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Application #:
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09375504
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Filing Dt:
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08/17/1999
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Title:
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METHOD FOR ETCHING MEMORY GATE STACK USING THIN RESIST LAYER
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|
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Patent #:
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Issue Dt:
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06/19/2001
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Application #:
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09376658
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Filing Dt:
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08/18/1999
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Title:
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METHOD FOR PROTECTING GATE EDGES FROM CHARGE GAIN/LOSS IN SEMICONDUCTOR DEVICE
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|
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Patent #:
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Issue Dt:
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10/26/2004
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Application #:
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09376659
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Filing Dt:
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08/18/1999
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Title:
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METHOD FOR PROTECTING GATE EDGES FROM CHARGE GAIN/LOSS IN SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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06/26/2001
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Application #:
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09377183
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Filing Dt:
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08/19/1999
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Title:
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NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE INCLUDING ASSYMETRICALLY NITROGEN DOPED GATE OXIDE
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|
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Patent #:
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Issue Dt:
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07/11/2000
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Application #:
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09379479
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Filing Dt:
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08/23/1999
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Title:
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FLASH MEMORY ARCHITECTURE EMPLOYING THREE LAYER METAL INTERCONNECT FOR WORD LINE DECODING
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Patent #:
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Issue Dt:
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06/05/2001
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Application #:
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09385550
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Filing Dt:
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08/30/1999
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Title:
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USING POLYSILICON FUSE FOR IC PROGRAMMING
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Patent #:
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Issue Dt:
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06/25/2002
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Application #:
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09387018
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Filing Dt:
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08/31/1999
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Title:
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CONTINOUS CAPACITOR DIVIDER SAMPLED REGULATION SCHEME
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Patent #:
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Issue Dt:
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07/09/2002
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Application #:
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09387421
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Filing Dt:
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08/31/1999
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Title:
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EMBEDDED METHODOLOGY TO PROGRAM/ERASE REFERENCE CELLS USED IN SENSING FLASH CELLS
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Patent #:
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Issue Dt:
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06/10/2003
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Application #:
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09387710
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Filing Dt:
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08/30/1999
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Title:
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INTEGRATED CIRCUIT HAVING OPTIMIZED GATE COUPLING CAPACITANCE
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