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Patent #:
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Issue Dt:
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05/20/2003
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Application #:
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09644359
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Filing Dt:
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08/23/2000
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Title:
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PHYSICAL MEMORY LAYOUT WITH VARIOUS SIZED MEMORY SECTORS
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Patent #:
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Issue Dt:
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04/23/2002
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Application #:
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09645623
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Filing Dt:
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08/24/2000
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Title:
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Fast-erase memory devices and method for reducing erasing time in a memory device
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Patent #:
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Issue Dt:
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05/28/2002
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Application #:
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09648077
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Filing Dt:
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08/25/2000
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Title:
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METHOD OF FORMING ONO FLASH MEMORY DEVICES USING RAPID THERMAL OXIDATION
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Patent #:
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Issue Dt:
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03/26/2002
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Application #:
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09648361
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Filing Dt:
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08/25/2000
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Title:
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METHOD OF FORMING ONO FLASH MEMORY DEVICES USING LOW ENERGY NITROGEN IMPLANTATION
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Patent #:
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Issue Dt:
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02/12/2002
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Application #:
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09649027
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Filing Dt:
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08/28/2000
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Title:
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METHOD OF MAKING TUNGSTEN GATE MOS TRANSISTOR AND MEMORY CELL BY ENCAPSULATING
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Patent #:
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Issue Dt:
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07/09/2002
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Application #:
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09651684
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Filing Dt:
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08/30/2000
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Title:
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Semiconductor structure
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Patent #:
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Issue Dt:
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05/13/2003
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Application #:
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09651704
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Filing Dt:
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08/31/2000
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Title:
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BIT-LINE OXIDATION BY REMOVING ONO OXIDE PRIOR TO BIT-LINE IMPLANT
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Patent #:
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Issue Dt:
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08/20/2002
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Application #:
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09652132
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Filing Dt:
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08/31/2000
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Title:
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METHOD OF DEGASSING LOW K DIELECTRIC FOR METAL DEPOSITION
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Patent #:
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Issue Dt:
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08/06/2002
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Application #:
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09652136
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Filing Dt:
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08/31/2000
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Title:
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NON-VOLATILE MEMORY DEVICE WITH ENCAPSULATED TUNGSTEN GATE AND METHOD OF MAKING SAME
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Patent #:
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Issue Dt:
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10/02/2001
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Application #:
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09652742
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Filing Dt:
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08/31/2000
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Title:
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Method and apparatus for eliminating false data in a page mode memory device
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Patent #:
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Issue Dt:
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06/18/2002
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Application #:
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09654831
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Filing Dt:
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09/01/2000
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Title:
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ARRANGEMENT FOR PROGRAMMING SELECTED DEVICE REGISTERS DURING INITIALIZATION FROM AN EXTERNAL MEMORY
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Patent #:
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Issue Dt:
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07/01/2003
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Application #:
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09654965
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Filing Dt:
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09/05/2000
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Title:
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METHOD OF MICRO-ARCHITECTURAL IMPLEMENTATION OF INTERFACE BETWEEN BIST STATE MACHINE AND TESTER INTERFACE TO ENABLE BIST CYCLING
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Patent #:
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Issue Dt:
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09/16/2003
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Application #:
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09655335
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Filing Dt:
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09/05/2000
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Title:
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METHOD OF MICRO-ARCHITECTURAL IMPLEMENTATION ON BIST FRONTED STATE MACHINE UTILIZING 'DEATH LOGIC' STATE TRANSITION FOR AREA MINIMIZATION
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Patent #:
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Issue Dt:
|
04/30/2002
|
Application #:
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09656675
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Filing Dt:
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09/07/2000
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Title:
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USING A NEGATIVE GATE ERASE TO INCREASE THE CYCLING ENDURANCE OF A NON-VOLATILE MEMORY CELL WITH AN OXIDE-NITRIDE-OXIDE (ONO) STRUCTURE
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Patent #:
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Issue Dt:
|
03/12/2002
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Application #:
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09657029
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Filing Dt:
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09/07/2000
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Title:
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Using negative gate erase voltage to simultaneously erase two bits from a non-volatile memory cell with an oxide-nitride-oxide (ONO) gate structure
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Patent #:
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Issue Dt:
|
04/15/2003
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Application #:
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09657143
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Filing Dt:
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09/07/2000
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Title:
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USING A NEGATIVE GATE ERASE VOLTAGE APPLIED IN STEPS OF DECREASING AMOUNTS TO REDUCE ERASE TIME FOR A NON-VOLATILE MEMORY CELL WITH AN OXIDE-NITRIDE-OXIDE (ONO) STRUCTURE
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Patent #:
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Issue Dt:
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07/24/2001
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Application #:
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09661356
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Filing Dt:
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09/14/2000
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Title:
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Output buffer for external voltage
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Patent #:
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Issue Dt:
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08/14/2001
|
Application #:
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09661358
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Filing Dt:
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09/14/2000
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Title:
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Chip enable input buffer
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Patent #:
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Issue Dt:
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11/25/2003
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Application #:
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09662791
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Filing Dt:
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09/15/2000
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Title:
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SIMULTANEOUS EXECUTION COMMAND MODES IN A FLASH MEMORY DEVICE
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Patent #:
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Issue Dt:
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03/05/2002
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Application #:
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09663552
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Filing Dt:
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09/18/2000
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Title:
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System and method for tracking sensing speed by an equalization pulse for a high density flash memory device
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Patent #:
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Issue Dt:
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10/08/2002
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Application #:
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09663765
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Filing Dt:
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09/18/2000
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Title:
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VARIABLE SECTOR SIZE FOR A HIGH DENSITY FLASH MEMORY DEVICE
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Patent #:
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Issue Dt:
|
09/04/2001
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Application #:
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09663909
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Filing Dt:
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09/18/2000
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Title:
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Address transition detector architecture for a high density flash memory device
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Patent #:
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Issue Dt:
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02/19/2002
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Application #:
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09664636
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Filing Dt:
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09/19/2000
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Title:
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Method and apparatus for determining the robustness of memory cells to alpha-particle/cosmic ray induced soft errors
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Patent #:
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Issue Dt:
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05/04/2004
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Application #:
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09664819
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Filing Dt:
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09/19/2000
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Title:
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INTEGRATION OF EMBEDDED AND TEST MODE TIMER
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Patent #:
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Issue Dt:
|
03/04/2003
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Application #:
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09665916
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Filing Dt:
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09/20/2000
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Title:
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NAND ARRAY STRUCTURE AND METHOD WITH BURIED LAYER
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Patent #:
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Issue Dt:
|
04/09/2002
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Application #:
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09667347
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Filing Dt:
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09/22/2000
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Title:
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Serial sequencing of automatic program disturb erase verify during a fast erase mode
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Patent #:
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Issue Dt:
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01/14/2003
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Application #:
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09667686
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Filing Dt:
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09/22/2000
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Title:
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MULTIPLE CHANNEL IMPLANTATION TO FORM RETROGRADE CHANNEL PROFILE AND TO ENGINEER THRESHOLD VOLTAGE AND SUB-SURFACE PUNCH-THROUGH
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Patent #:
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Issue Dt:
|
11/27/2001
|
Application #:
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09667891
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Filing Dt:
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09/22/2000
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Title:
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Application of external voltage during array VT testing
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Patent #:
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|
Issue Dt:
|
08/20/2002
|
Application #:
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09668100
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Filing Dt:
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09/22/2000
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Title:
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NEGATIVE VOLTAGE REGULATION
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Patent #:
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Issue Dt:
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05/21/2002
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Application #:
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09670229
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Filing Dt:
|
09/25/2000
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Title:
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PROCESS FOR FABRICATING SHALLOW POCKET REGIONS IN A NON-VOLATILE SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
|
06/04/2002
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Application #:
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09675372
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Filing Dt:
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09/29/2000
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Title:
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POWER-SAVING MODES FOR MEMORIES
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Patent #:
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Issue Dt:
|
09/11/2001
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Application #:
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09675940
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Filing Dt:
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09/29/2000
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Title:
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Method and apparatus for continuously regulating a charge pump output voltage using a capacitor divider
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Patent #:
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Issue Dt:
|
11/02/2004
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Application #:
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09676623
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Filing Dt:
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10/02/2000
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Title:
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I/O BASED COLUMN REDUNDANCY FOR VIRTUAL GROUND WITH 2-BIT CELL FLASH MEMORY
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Patent #:
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Issue Dt:
|
10/30/2001
|
Application #:
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09676902
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Filing Dt:
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10/02/2000
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Title:
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Architecture for a dual-bank page mode memory with redundancy
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Patent #:
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Issue Dt:
|
06/04/2002
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Application #:
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09680344
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Filing Dt:
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10/05/2000
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Title:
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Wordline driver for flash memory read mode
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Patent #:
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Issue Dt:
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12/31/2002
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Application #:
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09684694
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Filing Dt:
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10/04/2000
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Title:
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USING A LOW DRAIN BIAS DURING ERASE VERIFY TO ENSURE COMPLETE REMOVAL OF RESIDUAL CHARGE IN THE NITRIDE IN SONOS NON-VOLATILE MEMORIES
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Patent #:
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Issue Dt:
|
08/07/2001
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Application #:
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09685968
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Filing Dt:
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10/10/2000
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Title:
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Method for forming self-aligned contacts and local interconnects using self-aligned local interconnects
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Patent #:
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Issue Dt:
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11/19/2002
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Application #:
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09685972
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Filing Dt:
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10/10/2000
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Title:
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METHOD FOR FORMING SELF-ALIGNED CONTACTS AND LOCAL INTERCONNECTS USING DECOUPLED LOCAL INTERCONNECT PROCESS
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Patent #:
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Issue Dt:
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11/05/2002
|
Application #:
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09686685
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Filing Dt:
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10/11/2000
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Title:
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SELECT TRANSISTOR ARCHITECTURE FOR A VIRTUAL GROUND NON-VOLATILE MEMORY CELL ARRAY
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Patent #:
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Issue Dt:
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04/02/2002
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Application #:
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09686686
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Filing Dt:
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10/11/2000
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Title:
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Selective erasure of a non-volatile memory cell of a flash memory device
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Patent #:
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Issue Dt:
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02/19/2002
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Application #:
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09686693
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Filing Dt:
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10/11/2000
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Title:
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Selective erasure of a non-volatile memory cell of a flash memory device
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Patent #:
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Issue Dt:
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03/25/2003
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Application #:
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09688504
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Filing Dt:
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10/16/2000
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Title:
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PROCESS FOR FABRICATING A NON-VOLATILE MEMORY DEVICE
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Patent #:
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Issue Dt:
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06/24/2003
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Application #:
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09688936
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Filing Dt:
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10/16/2000
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Title:
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SIDEWALL NROM AND METHOD OF MANUFACTURE THEREOF FOR NON-VOLATILE MEMORY CELLS
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Patent #:
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Issue Dt:
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04/16/2002
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Application #:
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09689036
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Filing Dt:
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10/12/2000
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Title:
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Two side decoding of a memory array
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Patent #:
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Issue Dt:
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05/20/2003
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Application #:
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09689144
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Filing Dt:
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10/11/2000
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Title:
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METHOD FOR SIMULTANEOUS DEPOSITION AND SPUTTERING OF TEOS AND DEVICE THEREBY FORMED
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Patent #:
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Issue Dt:
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05/20/2003
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Application #:
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09689714
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Filing Dt:
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10/13/2000
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Title:
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A NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING A CHARGE STORING INSULATION FILM AND DATA HOLDING METHOD THEREFOR
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Patent #:
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Issue Dt:
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02/12/2002
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Application #:
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09690554
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Filing Dt:
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10/17/2000
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Title:
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Word line decoding architecture in a flash memory
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Patent #:
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Issue Dt:
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03/25/2003
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Application #:
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09691643
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Filing Dt:
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10/18/2000
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Title:
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METHOD OF FORMING NARROW INSULATING SPACERS FOR USE IN REDUCING MINIMUM COMPONENT SIZE
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Patent #:
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Issue Dt:
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06/26/2001
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Application #:
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09692881
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Filing Dt:
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10/23/2000
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Title:
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Automatic program disturb with intelligent soft programming for flash cells
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Patent #:
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Issue Dt:
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09/17/2002
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Application #:
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09693649
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Filing Dt:
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10/21/2000
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Title:
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FEEDBACK METHOD TO OPTIMIZE ELECTRIC FIELD DURING CHANNEL ERASE OF FLASH MEMORY DEVICES
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Patent #:
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Issue Dt:
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05/15/2001
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Application #:
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09693650
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Filing Dt:
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10/21/2000
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Title:
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Self-limiting multi-level programming states
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Patent #:
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Issue Dt:
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03/26/2002
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Application #:
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09694688
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Filing Dt:
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10/23/2000
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Title:
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Low column leakage NOR flash array - single cell implementation
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Patent #:
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Issue Dt:
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07/31/2001
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Application #:
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09694729
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Filing Dt:
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10/23/2000
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Title:
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Method of programming a non-volatile memory cell using a current limiter
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Patent #:
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Issue Dt:
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09/18/2001
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Application #:
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09696652
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Filing Dt:
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10/25/2000
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Title:
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Power saving on the fly during reading of data from a memory device
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Patent #:
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Issue Dt:
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12/18/2001
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Application #:
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09697810
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Filing Dt:
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10/26/2000
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Title:
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Positive gate erasure for non-volatile memory cells
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Patent #:
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Issue Dt:
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12/18/2001
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Application #:
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09697813
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Filing Dt:
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10/26/2000
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Title:
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Intelligent ramped gate and ramped drain erasure for non-volatile memory cells
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Patent #:
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Issue Dt:
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12/03/2002
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Application #:
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09697814
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Filing Dt:
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10/26/2000
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Title:
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METHOD OF ERASING A NON-VOLATILE MEMORY CELL USING A SUBSTRATE BIAS
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Patent #:
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Issue Dt:
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08/20/2002
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Application #:
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09697815
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Filing Dt:
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10/26/2000
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Title:
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METHOD OF PROGRAMMING A NON-VOLATILE MEMORY CELL USING A SUBSTRATE BIAS
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Patent #:
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Issue Dt:
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02/04/2003
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Application #:
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09698485
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Filing Dt:
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10/30/2000
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Title:
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THIN OXIDE ANTI-FUSE
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Patent #:
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Issue Dt:
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01/14/2003
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Application #:
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09698614
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Filing Dt:
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10/27/2000
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Title:
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MEMORY LINE DISCHARGE BEFORE SENSING
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Patent #:
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Issue Dt:
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12/31/2002
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Application #:
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09699531
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Filing Dt:
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10/30/2000
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Title:
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METHOD FOR SELECTIVE REMOVAL OF ONO LAYER
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Patent #:
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Issue Dt:
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11/25/2003
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Application #:
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09699711
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Filing Dt:
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10/30/2000
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Title:
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SOURCE SIDE BORON IMPLANT AND DRAIN SIDE MDD IMPLANT FOR DEEP SUB 0.18 MICRON FLASH MEMORY
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Patent #:
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Issue Dt:
|
02/25/2003
|
Application #:
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09699972
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Filing Dt:
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10/30/2000
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Title:
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SOURCE SIDE BORON IMPLANTING AND DIFFUSING DEVICE ARCHITECTURE FOR DEEP SUB 0.18 MICRON FLASH MEMORY
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Patent #:
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Issue Dt:
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08/27/2002
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Application #:
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09704026
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Filing Dt:
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11/01/2000
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Title:
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PHOTORESIST SPACER PROCESS SIMPLIFICATION TO ELIMINATE THE STANDARD POLYSILICON OR OXIDE SPACER PROCESS FOR FLASH MEMORY CIRCUITS
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Patent #:
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Issue Dt:
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08/21/2001
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Application #:
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09708982
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Filing Dt:
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11/01/2000
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Title:
|
Elimination of N+ implant from flash technologies by replacement with standard medium-doped-drain (Mdd) implant
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Patent #:
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Issue Dt:
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10/02/2001
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Application #:
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09712382
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Filing Dt:
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11/13/2000
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Title:
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Acceleration voltage implementation for a high density flash memory device
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Patent #:
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Issue Dt:
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02/17/2004
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Application #:
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09713390
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Filing Dt:
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11/15/2000
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Title:
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FLASH MEMORY CELL WITH MINIMIZED FLOATING GATE TO DRAIN/SOURCE OVERLAP FOR MINIMIZING CHARGE LEAKAGE
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Patent #:
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Issue Dt:
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10/23/2001
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Application #:
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09716659
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Filing Dt:
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11/20/2000
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Title:
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Double layer hard mask process to improve oxide quality for non-volatile flash memory products
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Patent #:
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Issue Dt:
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12/18/2001
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Application #:
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09717550
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Filing Dt:
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11/21/2000
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Title:
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Method and system for embedded chip erase verification
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Patent #:
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Issue Dt:
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07/15/2003
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Application #:
|
09718771
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Filing Dt:
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11/22/2000
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Title:
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STAGGERED BITLINE STRAPPING OF A NON-VOLATILE MEMORY CELL
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Patent #:
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Issue Dt:
|
10/29/2002
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Application #:
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09718986
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Filing Dt:
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11/22/2000
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|
Title:
|
METHOD AND SYSTEM FOR TESTING A SEMICONDUCTOR MEMORY DEVICE
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|
Patent #:
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Issue Dt:
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03/25/2003
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Application #:
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09721031
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Filing Dt:
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11/22/2000
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Title:
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STAGGERED BITLINE STRAPPING OF A NON-VOLATILE MEMORY CELL
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Patent #:
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Issue Dt:
|
07/09/2002
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Application #:
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09721066
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Filing Dt:
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11/22/2000
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Title:
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PROCESS FOR REDUCTION OF CAPACITANCE OF A BITLINE FOR A NON-VOLATILE MEMORY CELL
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Patent #:
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Issue Dt:
|
11/27/2001
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Application #:
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09721656
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Filing Dt:
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11/27/2000
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Title:
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2-Bit/cell type nonvolatile semiconductor memory
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Patent #:
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Issue Dt:
|
10/15/2002
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Application #:
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09723635
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Filing Dt:
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11/28/2000
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Title:
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SIMULTANEOUS FORMATION OF CHARGE STORAGE AND BITLINE TO WORDLINE ISOLATION
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Patent #:
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Issue Dt:
|
10/22/2002
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Application #:
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09723653
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Filing Dt:
|
11/28/2000
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Title:
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METHOD OF SIMULTANEOUS FORMATION OF BITLINE ISOLATION AND PERIPHEY OXIDE
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Patent #:
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Issue Dt:
|
09/16/2003
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Application #:
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09724675
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Filing Dt:
|
11/28/2000
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Title:
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MULTI-SET BLOCK ERASE
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Patent #:
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Issue Dt:
|
07/02/2002
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Application #:
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09725843
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Filing Dt:
|
11/30/2000
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Publication #:
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Pub Dt:
|
08/23/2001
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Title:
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METHOD OF FORMING A COMPOSITE INTERPOLY GATE DIELECTRIC
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Patent #:
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|
Issue Dt:
|
04/08/2003
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Application #:
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09727656
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Filing Dt:
|
11/30/2000
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Title:
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ERASE VERIFY MODE TO EVALUATE NEGATIVE VT'S
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|
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Patent #:
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|
Issue Dt:
|
11/29/2005
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Application #:
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09727714
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Filing Dt:
|
11/28/2000
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|
Title:
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FLASH NVROM DEVICES WITH UV CHARGE IMMUNITY
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Patent #:
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Issue Dt:
|
03/14/2006
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Application #:
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09728554
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Filing Dt:
|
12/01/2000
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Title:
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DUAL SPACER PROCESS FOR NON-VOLATILE MEMORY DEVICES
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|
|
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Patent #:
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Issue Dt:
|
10/08/2002
|
Application #:
|
09729388
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Filing Dt:
|
12/04/2000
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Publication #:
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Pub Dt:
|
12/13/2001
| | | | |
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Title:
|
POWER SAVING SCHEME FOR BURST MODE IMPLEMENTATION DURING READING OF DATA FROM A MEMORY DEVICE
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|
|
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Patent #:
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|
Issue Dt:
|
08/31/2004
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Application #:
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09732616
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Filing Dt:
|
12/07/2000
|
|
Title:
|
INTERNAL SELF-TEST CIRCUIT FOR A MEMORY ARRAY
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|
|
|
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Patent #:
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|
Issue Dt:
|
01/27/2004
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Application #:
|
09733252
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Filing Dt:
|
12/07/2000
|
|
Title:
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RELIABILITY MONITOR FOR A MEMORY ARRAY
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|
|
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Patent #:
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|
Issue Dt:
|
10/22/2002
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Application #:
|
09738760
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Filing Dt:
|
12/18/2000
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Publication #:
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Pub Dt:
|
09/13/2001
| | | | |
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Title:
|
METHOD FOR MANUFACTURING NON-VOLATILE SEMICONDUCTOR MEMORY AND NON-VOLATILE SEMICONDUCTOR MEMORY MANUFACTURED THEREBY
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|
|
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Patent #:
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|
Issue Dt:
|
07/22/2003
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Application #:
|
09739733
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Filing Dt:
|
12/18/2000
|
|
Title:
|
METHODS TO FORM REDUCED DIMENSION BIT-LINE ISOLATION IN THE MANUFACTURE OF NON-VOLATILE MEMORY DEVICES
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|
|
|
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Patent #:
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|
Issue Dt:
|
09/10/2002
|
Application #:
|
09764965
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Filing Dt:
|
01/17/2001
|
|
Title:
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ADAPTIVE REFERENCE CELLS FOR A MEMORY DEVICE
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|
|
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Patent #:
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|
Issue Dt:
|
10/01/2002
|
Application #:
|
09767341
|
Filing Dt:
|
01/23/2001
|
|
Title:
|
THREE METAL PROCESS FOR OPTIMIZING LAYOUT DENSITY
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|
|
|
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Patent #:
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|
Issue Dt:
|
09/03/2002
|
Application #:
|
09772600
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Filing Dt:
|
01/30/2001
|
|
Title:
|
FLASH MEMORY ERASE SPEED BY FLUORINE IMPLANT OR FLUORINATION
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/25/2002
|
Application #:
|
09774327
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Filing Dt:
|
01/31/2001
|
|
Publication #:
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|
Pub Dt:
|
06/28/2001
| | | | |
|
Title:
|
FLASH MEMORY DEVICE WITH MONITOR STRUCTURE FOR MONITORING SECOND GATE OVER-ETCH
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|
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Patent #:
|
|
Issue Dt:
|
08/14/2001
|
Application #:
|
09774509
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Filing Dt:
|
01/31/2001
|
|
Title:
|
Reduction of voltage stress across a gate oxide and across a junction within a high voltage transistor of an erasable memory device
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|
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Patent #:
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|
Issue Dt:
|
04/27/2004
|
Application #:
|
09777457
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Filing Dt:
|
02/06/2001
|
|
Publication #:
|
|
Pub Dt:
|
11/29/2001
| | | | |
|
Title:
|
METHOD AND SYSTEM FOR DECREASING THE SPACES BETWEEN WORDLINES
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/09/2002
|
Application #:
|
09779225
|
Filing Dt:
|
02/08/2001
|
|
Title:
|
PIGGYBACK PROGRAMMING USING GRADUATED STEPS FOR MULTI-LEVEL CELL FLASH MEMORY DESIGNS
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|
|
|
|
Patent #:
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|
Issue Dt:
|
12/17/2002
|
Application #:
|
09779764
|
Filing Dt:
|
02/08/2001
|
|
Title:
|
CONCURRENT PROGRAM RECONNAISSANCE WITH PIGGYBACK PULSES FOR MULTI-LEVEL CELL FLASH MEMORY DESIGNS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/2002
|
Application #:
|
09779792
|
Filing Dt:
|
02/08/2001
|
|
Title:
|
PIGGYBACK PROGRAMMING USING TIMING CONTROL FOR MULTI-LEVEL CELL FLASH MEMORY DESIGNS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/22/2003
|
Application #:
|
09779794
|
Filing Dt:
|
02/08/2001
|
|
Title:
|
PIGGYBACK PROGRAMMING USING AN EXTENDED FIRST PULSE FOR MULTI-LEVEL CELL FLASH MEMORY DESIGNS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/01/2003
|
Application #:
|
09779821
|
Filing Dt:
|
02/08/2001
|
|
Title:
|
PIGGYBACK PROGRAMMING USING VOLTAGE CONTROL FOR MULTI-LEVEL CELL FLASH MEMORY DESIGNS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2002
|
Application #:
|
09779864
|
Filing Dt:
|
02/08/2001
|
|
Title:
|
PROGRAM RECONNAISSANCE TO ELIMINATE VARIATIONS IN VT DISTRIBUTIONS OF MULTI-LEVEL CELL FLASH MEMORY DESIGNS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/30/2003
|
Application #:
|
09779884
|
Filing Dt:
|
02/08/2001
|
|
Title:
|
PIGGYBACK PROGRAMMING WITH STAIRCASE VERIFY FOR MULTI-LEVEL CELL FLASH MEMORY DESIGNS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/03/2002
|
Application #:
|
09784892
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Filing Dt:
|
02/15/2001
|
|
Title:
|
METHOD FOR PRODUCING A SHALLOW TRENCH ISOLATION FILLED WITH THERMAL OXIDE
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|
