Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 024616/0385 | |
| Pages: | 9 |
| | Recorded: | 06/30/2010 | | |
| Attorney Dkt #: | F127600 |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
8
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Patent #:
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NONE
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Issue Dt:
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Application #:
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12153792
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Filing Dt:
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05/23/2008
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Publication #:
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Pub Dt:
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11/26/2009
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Title:
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Output driver circuit for an integrated circuit
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Patent #:
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Issue Dt:
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06/05/2012
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Application #:
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12153793
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Filing Dt:
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05/23/2008
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Publication #:
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Pub Dt:
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11/26/2009
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Title:
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SIGNAL AMPLITUDE DISTORTION WITHIN AN INTEGRATED CIRCUIT
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Patent #:
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NONE
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Issue Dt:
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Application #:
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12153794
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Filing Dt:
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05/23/2008
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Publication #:
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Pub Dt:
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11/26/2009
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Title:
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Integrated circuit with inter-symbol interference self-testing
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Patent #:
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Issue Dt:
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08/03/2010
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Application #:
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12153795
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Filing Dt:
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05/23/2008
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Publication #:
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Pub Dt:
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11/26/2009
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Title:
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INTEGRATED CIRCUIT COMMUNICATION SELF-TESTING
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Patent #:
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Issue Dt:
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05/15/2012
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Application #:
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12153796
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Filing Dt:
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05/23/2008
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Publication #:
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Pub Dt:
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11/26/2009
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Title:
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PROGRAMMABLE DUTY CYCLE DISTORTION GENERATION CIRCUIT
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Patent #:
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NONE
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Issue Dt:
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Application #:
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12153801
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Filing Dt:
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05/23/2008
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Publication #:
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Pub Dt:
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11/26/2009
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Title:
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Programmable jitter generation circuit
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Patent #:
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Issue Dt:
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04/03/2012
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Application #:
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12153802
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Filing Dt:
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05/23/2008
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Publication #:
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Pub Dt:
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11/26/2009
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Title:
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ELECTROSTATIC DISCHARGE EVENT PROTECTION FOR AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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09/04/2012
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Application #:
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12153803
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Filing Dt:
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05/23/2008
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Publication #:
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Pub Dt:
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11/26/2009
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Title:
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METHOD OF PROCESSING SIGNAL DATA WITH CORRECTED CLOCK PHASE OFFSET
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Assignee
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| 2855 BOWERS AVENUE |
| SANTA CLARA, CALIFORNIA 95051 |
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Correspondence name and address
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ELSPETH CALLAHAN
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1100 G ST NW SUITE 420
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NATIONAL CORPORATE RESEARCH
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WASHINGTON, DC 20005
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