Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 024698/0224 | |
| Pages: | 3 |
| | Recorded: | 07/16/2010 | | |
| Attorney Dkt #: | 0265-10 |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
10
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Patent #:
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Issue Dt:
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09/20/1994
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Application #:
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08123524
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Filing Dt:
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09/17/1993
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Title:
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MEMORY ELEMENT WITH BIPOLAR TRANSISTORS IN RESETTABLE LATCH
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Patent #:
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Issue Dt:
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12/05/2000
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Application #:
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09216978
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Filing Dt:
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12/21/1998
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Title:
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"STACK ARRRANGEMENT FOR TWO SEMICONDUCTOR MEMORY CHIPS AND PRINTED BOARD FOR ACCEPTING A PURALITY OF SUCH STACK ARRANGEMENTS"
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Patent #:
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Issue Dt:
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03/23/2004
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Application #:
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10065128
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Filing Dt:
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09/19/2002
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Title:
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REFRESHING OF MULTI-PORT MEMORY IN INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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02/21/2006
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Application #:
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10065195
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Filing Dt:
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09/25/2002
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Publication #:
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Pub Dt:
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03/25/2004
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Title:
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REFRESH CONTROL CIRCUIT FOR ICS WITH A MEMORY ARRAY
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Patent #:
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Issue Dt:
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02/01/2005
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Application #:
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10376461
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Filing Dt:
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02/28/2003
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Publication #:
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Pub Dt:
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09/02/2004
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Title:
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SELECTIVE SILICIDATION SCHEME FOR MEMORY DEVICES
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Patent #:
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Issue Dt:
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08/01/2006
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Application #:
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10449580
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Filing Dt:
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05/30/2003
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Publication #:
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Pub Dt:
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12/25/2003
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Title:
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SYSTEM FOR TESTING A GROUP OF FUNCTIONALLY INDEPENDENT MEMORIES AND FOR REPLACING FAILING MEMORY WORDS
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Patent #:
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Issue Dt:
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08/02/2005
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Application #:
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10672393
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Filing Dt:
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09/25/2003
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Publication #:
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Pub Dt:
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03/31/2005
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Title:
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DIFFERENTIAL TO SINGLE-ENDED LOGIC CONVERTER
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Patent #:
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Issue Dt:
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06/26/2007
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Application #:
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10726990
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Filing Dt:
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12/03/2003
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Publication #:
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Pub Dt:
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08/05/2004
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Title:
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INTEGRATED MEMORY AND METHOD FOR TESTING AN INTEGRATED MEMORY
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Patent #:
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Issue Dt:
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08/28/2007
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Application #:
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11246046
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Filing Dt:
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10/07/2005
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Publication #:
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Pub Dt:
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04/27/2006
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Title:
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MEMORY CIRCUIT WITH FLEXIBLE BITLINE-RELATED AND/OR WORDLINE-RELATED DEFECT MEMORY CELL SUBSTITUTION
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Patent #:
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Issue Dt:
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04/08/2008
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Application #:
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11375565
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Filing Dt:
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03/15/2006
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Publication #:
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Pub Dt:
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09/21/2006
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Title:
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HEAT SINK FOR SURFACE-MOUNTED SEMICONDUCTOR DEVICES AND MOUNTING METHOD
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Assignee
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| 2-1, YAESU 2-CHOME |
| CHUO-KU, TOKYO, JAPAN 104-0028 |
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Correspondence name and address
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STEVEN M. GRUSKIN
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2100 PENNSYLVANIA AVENUE
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WASHINGTON, DC 20037
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