Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 024767/0324 | |
| Pages: | 5 |
| | Recorded: | 07/30/2010 | | |
| Attorney Dkt #: | 2222.880STR0 |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
5
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Patent #:
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Issue Dt:
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11/09/1993
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Application #:
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07761141
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Filing Dt:
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09/17/1991
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Title:
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BOUNDARY-SCAN INPUT CIRCUIT FOR A RESET PIN
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Patent #:
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Issue Dt:
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09/13/1994
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Application #:
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07761607
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Filing Dt:
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09/18/1991
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Title:
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BOUNDARY-SCAN ENABLE CELL WITH NON-CRITICAL ENABLE PATH
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Patent #:
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Issue Dt:
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11/29/1994
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Application #:
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07789553
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Filing Dt:
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11/08/1991
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Title:
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BUILT-IN SELF-TEST CIRCUIT
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Patent #:
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Issue Dt:
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12/27/1994
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Application #:
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07799507
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Filing Dt:
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11/27/1991
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Title:
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JTAG INSTRUCTION ERROR DETECTION
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Patent #:
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Issue Dt:
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11/09/1993
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Application #:
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08031077
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Filing Dt:
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03/11/1993
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Title:
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BIDIRECTIONAL BOUNDARY-SCAN CIRCUIT
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Assignee
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| 171 MAIN STREET |
| #271 |
| LOS ALTOS, CALIFORNIA 94022 |
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Correspondence name and address
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STERNE, KESSLER, GOLDSTEIN & FOX P.L.L.C
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1100 NEW YORK AVENUE, N.W.
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WASHINGTON, DC 20005
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