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Patent #:
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Issue Dt:
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11/02/1993
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Application #:
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07962451
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Filing Dt:
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10/16/1992
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Title:
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METHOD AND APPARATUS FOR MONOTONIC ALGORITHMIC DIGITAL-TO-ANALOG AND ANALOG-TO-DIGITAL CONVERSION
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Patent #:
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Issue Dt:
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01/23/2001
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Application #:
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08080156
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Filing Dt:
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06/17/1993
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Title:
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Method and Apparatus For Generating Non-Redundant Symbolic Debug Information In Computer Programs
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Patent #:
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Issue Dt:
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12/26/1995
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Application #:
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08146660
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Filing Dt:
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11/02/1993
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Title:
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METHOD AND APPARATUS FOR LONG-TERM MULTI-VALUED STORAGE IN DYNAMIC ANALOG MEMORY
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Patent #:
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Issue Dt:
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05/06/1997
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Application #:
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08399966
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Filing Dt:
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03/07/1995
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Title:
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A SEMICONDUCTOR STRUCTURE FOR LONG TERM LEARNING
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Patent #:
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Issue Dt:
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03/03/1998
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Application #:
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08557474
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Filing Dt:
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11/14/1995
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Title:
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GATE ARRAY CELL ARCHITECTURE AND ROUTING SCHEME
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Patent #:
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Issue Dt:
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10/20/1998
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Application #:
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08690198
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Filing Dt:
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07/26/1996
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Title:
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THREE-TERMINAL SILICON SYNAPTIC DEVICE
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Patent #:
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Issue Dt:
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02/23/1999
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Application #:
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08721261
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Filing Dt:
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09/26/1996
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Title:
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AUTOZEROING FLOATING-GATE AMPLIFIER
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Patent #:
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Issue Dt:
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07/13/1999
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Application #:
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08747858
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Filing Dt:
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11/13/1996
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Title:
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INTEGRATED CIRCUIT CELL ARCHITECTURE AND ROUTING SCHEME
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Patent #:
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Issue Dt:
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04/18/2000
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Application #:
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08795580
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Filing Dt:
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02/05/1997
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Title:
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MODULE-BASED LOGIC ARCHITECTURE AND DESIGN FLOW FOR VLSI IMPLEMENTATION
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Patent #:
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Issue Dt:
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11/23/1999
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Application #:
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08845018
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Filing Dt:
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04/22/1997
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Title:
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HOLE IMPACT IONIZATION MECHANISM OF HOT ELECTRON INJECTION AND FOUR-TERMINAL P-FET SEMICONDUCTOR STRUCTURE FOR LONG-TERM LEARNING
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Patent #:
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Issue Dt:
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04/27/1999
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Application #:
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08853875
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Filing Dt:
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05/09/1997
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Title:
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INTEGRATED CIRCUIT CELL ARCHITECTURE AND ROUTING SCHEME
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Patent #:
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Issue Dt:
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04/27/1999
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Application #:
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08882717
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Filing Dt:
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06/25/1997
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Title:
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A PMOS ANALOG EEPROM CELL
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Patent #:
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Issue Dt:
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07/13/1999
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Application #:
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08917006
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Filing Dt:
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08/21/1997
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Title:
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REDUCED AREA GATE ARRAY CELL DESIGN BASED ON SHIFTED PLACEMENT OF ALTERNATE ROWS OF CELLS
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Patent #:
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Issue Dt:
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07/18/2000
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Application #:
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08933552
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Filing Dt:
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09/19/1997
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Title:
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POWER AND SIGNAL ROUTING TECHNIQUE FOR GATE ARRAY DESIGN
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Patent #:
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Issue Dt:
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06/22/1999
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Application #:
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09088655
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Filing Dt:
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06/01/1998
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Title:
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METHOD FOR IMPLEMENTING A LEARNING FUNCTION
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Patent #:
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Issue Dt:
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11/16/1999
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Application #:
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09189595
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Filing Dt:
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11/10/1998
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Title:
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AUTOZEROING FLOATING-GATE AMPLIFIER
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Patent #:
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Issue Dt:
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11/07/2000
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Application #:
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09201327
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Filing Dt:
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11/30/1998
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Title:
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A PMOS ANALOG EEPROM CELL
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Patent #:
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Issue Dt:
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09/26/2000
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Application #:
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09201677
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Filing Dt:
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11/30/1998
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Title:
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SEMICONDUCTOR STRUCTURE FOR LONG-TERM LEARNING
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Patent #:
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Issue Dt:
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07/04/2000
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Application #:
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09226777
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Filing Dt:
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01/06/1999
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Title:
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DUAL PORT MEMORY DEVICE WITH VERTICAL SHIELDING
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Patent #:
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Issue Dt:
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08/15/2000
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Application #:
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09227501
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Filing Dt:
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01/06/1999
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Title:
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MEMORY ARRAY WITH A SIMULTANEOUS READ OR SIMULTANEOUS WRITE PORTS
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Patent #:
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Issue Dt:
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05/01/2001
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Application #:
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09306069
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Filing Dt:
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05/06/1999
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Title:
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DATA PROCESSING CIRCUIT WITH CACHE MEMORY AND CACHE MANAGEMENT UNIT FOR ARRANGING SELECTED STORAGE LOCATION IN THE CACHE MEMORY FOR REUSE DEPENDENT ON A POS ITION OF PARTICULAR ADDRESS RELATIVE TO CURRENT ADDRESS
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Patent #:
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Issue Dt:
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09/24/2002
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Application #:
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09313244
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Filing Dt:
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05/17/1999
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Title:
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SYNCHRONOUS MEMORY SYSTEM WITH AUTOMATIC BURST MODE SWITCHING AS A FUNCTION OF THE SELECTED BUS MASTER
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Patent #:
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Issue Dt:
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07/04/2000
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Application #:
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09347372
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Filing Dt:
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07/06/1999
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Title:
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MULTI-BANK MEMORY WITH WORD-LINE BANKING
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Patent #:
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Issue Dt:
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07/18/2000
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Application #:
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09347955
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Filing Dt:
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07/06/1999
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Title:
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MULTI-BANK MEMORY WITH WORD-LINE BANKING, BIT-LINE BANKING AND I/O MULTIPLEXING UTILIZING TILABLE INTERCONNECTS
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Patent #:
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Issue Dt:
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01/04/2005
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Application #:
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09351767
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Filing Dt:
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07/12/1999
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Title:
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DUAL -HEIGHT CELL WITH VARIABLE WIDTH POWER RAIL ARCHITECTURE
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Patent #:
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Issue Dt:
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04/23/2002
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Application #:
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09408137
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Filing Dt:
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09/29/1999
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Title:
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ANALOG COMPUTATION DEVICE USING SEPARATED ANALOG SIGNALS, EACH HAVING A SPECIFIED AMOUNT OF RESOLUTION, AND SIGNAL RESTORATION DEVICES
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Patent #:
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Issue Dt:
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03/01/2005
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Application #:
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09418663
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Filing Dt:
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10/14/1999
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Title:
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METHOD AND APPARATUS FOR MANAGING THE CONFIGURATION AND FUNCTIONALITY OF A SEMICONDUCTOR DESIGN
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Patent #:
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Issue Dt:
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07/31/2001
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Application #:
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09439837
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Filing Dt:
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11/12/1999
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Title:
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SYSTEM AND METHOD FOR TESTING MULTIPLE PORT MEMORY DEVICES
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Patent #:
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Issue Dt:
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03/26/2002
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Application #:
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09455045
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Filing Dt:
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12/06/1999
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Title:
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ARCHITECTURE WITH MULTI-INSTANCE REDUNDANCY IMPLEMENTATION
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Patent #:
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03/12/2002
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Application #:
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09510692
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02/23/2000
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Title:
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Reduced latency row selection circuit and method
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Patent #:
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Issue Dt:
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05/06/2003
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Application #:
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09523871
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Filing Dt:
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03/13/2000
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Title:
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METHOD AND APPARATUS FOR JUMP CONTROL IN A PIPELINED PROCESSOR
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Patent #:
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Issue Dt:
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10/30/2001
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Application #:
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09528660
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Filing Dt:
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03/20/2000
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Title:
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Multi-bank memory with word-line banking, bit-line banking and i/o multiplexing utilizing tilable interconnects
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Patent #:
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Issue Dt:
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05/22/2001
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Application #:
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09542033
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Filing Dt:
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04/03/2000
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Title:
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Centrally decoded divided wordline (DWL) memory architecture
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Patent #:
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Issue Dt:
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09/09/2003
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Application #:
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09588802
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Filing Dt:
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06/06/2000
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Title:
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GATE ARRAY ARCHITECTURE USING ELEVATED METAL LEVELS FOR CUSTOMIZATION
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Patent #:
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09/03/2002
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09588804
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Filing Dt:
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06/06/2000
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Title:
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ROUTING DRIVEN, METAL PROGRAMMABLE INTEGRATED CIRCUIT ARCHITECTURE WITH MULTIPLE TYPES OF CORE CELLS
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Patent #:
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Issue Dt:
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10/15/2002
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Application #:
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09590619
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Filing Dt:
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06/08/2000
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Title:
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COMPILABLE BLOCK CLEAR MECHANISM ON PER I/O BASIS FOR HIGH-SPEED MEMORY
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Patent #:
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06/19/2001
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Application #:
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09605221
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06/28/2000
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Title:
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Fast full signal differential output path circuit for high-speed memory
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Patent #:
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Issue Dt:
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08/28/2001
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Application #:
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09671456
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Filing Dt:
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09/27/2000
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Title:
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Self-timed clock circuitry in a multi-bank memory instance using a common timing synchronization node
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Patent #:
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09/18/2001
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Application #:
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09689352
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10/12/2000
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Title:
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Hierarchical sense amp and write driver circuitry for compilable memory
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09/17/2002
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09699059
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10/27/2000
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Title:
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PMOS ANALOG EEPROM CELL
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10/15/2002
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Application #:
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09706314
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11/04/2000
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Title:
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CIRCUITRY FOR RESETTING MEMORY WITHOUT A WRITE CYCLE
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05/21/2002
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09728377
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11/28/2000
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Title:
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FAST READ/WRITE CYCLE MEMORY DEVICE HAVING A SELF-TIMED READ/WRITE CONTROL CIRCUIT
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07/23/2002
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09750949
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12/28/2000
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SYSTEM AND METHOD FOR INCREASING PERFORMANCE IN A COMPILABLE READ-ONLY MEMORY (ROM)
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05/07/2002
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09773319
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01/31/2001
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ROW AND COLUMN ACCESSIBLE MEMORY WITH A BUILT-IN MULTIPLEX
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01/17/2006
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09801241
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03/07/2001
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01/09/2003
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Title:
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MEMORY INTERFACE AND METHOD OF INTERFACING BETWEEN FUNCTIONAL ENTITIES
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01/09/2007
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09805423
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03/13/2001
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12/27/2001
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DIFFERENCE ENGINE METHOD AND APPARATUS
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05/23/2006
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09808469
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03/14/2001
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01/31/2002
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METHOD AND APPARATUS FOR PROCESSOR CODE OPTIMIZATION USING CODE COMPRESSION
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11/07/2006
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09808612
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03/14/2001
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12/27/2001
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METHOD AND APPARATUS FOR DEBUGGING PROGRAMS IN A DISTRIBUTED ENVIRONMENT
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05/28/2002
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09810817
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03/16/2001
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MEMORY HAVING A REDUNDANCY SCHEME TO ALLOW ONE FUSE TO BLOW PER FAULTY MEMORY COLUMN
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05/17/2005
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09870918
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05/31/2001
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12/05/2002
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POWER AND FREQUENCY ADJUSTABLE UART DEVICE
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01/25/2005
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09886300
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06/21/2001
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02/06/2003
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METHOD AND APPARATUS FOR IMPLEMENTING A SINGLE CYCLE OPERATION IN A DATA PROCESSING SYSTEM
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04/26/2005
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09886577
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06/21/2001
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SIMULTANEOUS ACCESS AND CACHE LOADING IN A HIERARCHICALLY ORGANIZED MEMORY CIRCUIT
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08/12/2003
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09886701
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06/21/2001
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03/27/2003
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SIMULATION METHOD AND COMPILER FOR HARDWARE/SOFTWARE PROGRAMMING
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02/11/2003
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09895896
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06/29/2001
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METHOD AND APPARATUS TO CHANGE THE AMOUNT OF REDUNDANT MEMORY COLUMN AND FUSES ASSOCIATED WITH A MEMORY DEVICE
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08/26/2003
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09912146
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07/24/2001
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01/30/2003
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METHOD AND SYSTEM USING A COMMON RESET AND A SLOWER RESET CLOCK
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12/16/2003
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09929652
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08/13/2001
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METHOD AND APPARATUS FOR TRIMMING HIGH-RESOLUTION DIGITAL-TO-ANALOG CONVERTER
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08/16/2005
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08/29/2001
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03/06/2003
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SYSTEM FOR BUS MONITORING USING A RECONFIGURABLE BUS MONITOR WHICH IS ADAPTED TO REPORT BACK TO CPU IN RESPONSE TO DETECTING CERTAIN SELECTED EVENTS
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03/28/2006
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09955704
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09/19/2001
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03/20/2003
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DATA COMMUNICATION BUS TRAFFIC GENERATOR ARRANGEMENT
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05/18/2004
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09/19/2001
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MULTI-BANK MEMORY WITH WORD-LINE BANKING, BIT-LINE BANKING AND I/O MULTIPLEXING UTILIZING TILABLE INTERCONNECTS
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10/24/2006
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09/24/2001
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03/27/2007
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10/18/2001
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SYSTEM AND METHOD FOR MEMORY COMPILER CHARACTERIZATION
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10/29/2002
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10002568
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11/01/2001
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LOW POWER READ CIRCUITRY FOR A MEMORY CIRCUIT BASED ON CHARGE REDISTRIBUTION BETWEEN BITLINES AND SENSE AMPLIFIER
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06/26/2007
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10083241
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02/25/2002
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05/18/2004
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03/05/2002
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SYSTEM AND METHOD FOR MEMORY CHARACTERIZATION
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04/29/2003
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10099750
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03/15/2002
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10/24/2002
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03/07/2006
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10125816
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04/18/2002
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12/19/2002
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Issue Dt:
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07/01/2003
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Application #:
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10128441
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Filing Dt:
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04/23/2002
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Title:
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SYSTEM AND METHOD FOR INCREASING PERFORMANCE IN A COMPILABLE READ-ONLY MEMORY (ROM)
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Patent #:
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Issue Dt:
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03/23/2004
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Application #:
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10142523
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Filing Dt:
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05/08/2002
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Title:
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SYSTEM AND METHOD FOR BIT LINE SHARING
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Patent #:
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Issue Dt:
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08/15/2006
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Application #:
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10144020
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Filing Dt:
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05/13/2002
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Title:
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EMBEDDED TEST AND REPAIR SCHEME AND INTERFACE FOR COMPILING A MEMORY ASSEMBLY WITH REDUNDANCY IMPLEMENTATION
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Patent #:
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Issue Dt:
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06/01/2004
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Application #:
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10146523
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Filing Dt:
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05/15/2002
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Title:
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RADIATION-HARDENED STATIC MEMORY CELL USING ISOLATION TECHNOLOGY
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Patent #:
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Issue Dt:
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04/06/2004
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Application #:
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10165146
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Filing Dt:
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06/05/2002
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Title:
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METHOD AND APPARATUS FOR IMPLEMENTING A DATA PROCESSOR ADAPTED FOR TURBO DECODING
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Patent #:
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Issue Dt:
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12/09/2003
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Application #:
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10191779
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Filing Dt:
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07/08/2002
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Title:
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HIGH VOLTAGE CHARGE PUMP CIRCUIT
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Patent #:
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Issue Dt:
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11/15/2005
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Application #:
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10192773
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Filing Dt:
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07/09/2002
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Publication #:
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Pub Dt:
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11/06/2003
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Title:
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FLOATING-GATE SEMICONDUCTOR STRUCTURES
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Patent #:
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Issue Dt:
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11/11/2003
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Application #:
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10210525
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Filing Dt:
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07/31/2002
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Title:
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METHOD AND APPARATUS TO REDUCE THE AMOUNT OF REDUNDANT MEMORY COLUMN AND FUSES ASSOCIATED WITH A MEMORY DEVICE
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Patent #:
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Issue Dt:
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09/26/2006
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Application #:
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10216598
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Filing Dt:
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08/09/2002
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Title:
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SYSTEM AND METHOD FOR PROVIDING ADJUSTABLE READ MARGINS IN A SEMICONDUCTOR MEMORY
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Patent #:
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Issue Dt:
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07/22/2003
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Application #:
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10223499
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Filing Dt:
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08/19/2002
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Title:
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BUILT-IN PRECISION SHUTDOWN APPARATUS FOR EFFECTUATING SELF-REFERENCED ACCESS TIMING SCHEME
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Patent #:
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Issue Dt:
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02/01/2005
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Application #:
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10226380
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Filing Dt:
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08/22/2002
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Title:
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MEMORY CELL SENSING WITH LOW NOISE GENERATION
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Patent #:
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Issue Dt:
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12/12/2006
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Application #:
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10236248
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Filing Dt:
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09/05/2002
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Title:
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APPARATUS, METHOD, AND SYSTEM HAVING A PIN TO ACTIVATE THE SELF-TEST AND REPAIR INSTRUCTIONS
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Patent #:
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Issue Dt:
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12/12/2006
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Application #:
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10236555
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Filing Dt:
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09/06/2002
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Title:
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APPARATUS, METHOD, AND SYSTEM TO ALLOCATE REDUNDANT COMPONENTS WITH SUBSETS OF THE REDUNDANT COMPONENTS
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Patent #:
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Issue Dt:
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02/08/2005
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Application #:
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10245183
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Filing Dt:
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09/16/2002
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Publication #:
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Pub Dt:
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03/18/2004
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Title:
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METHOD AND APPARATUS FOR PREVENTING OVERTUNNELING IN PFET-BASED NONVOLATILE MEMORY CELLS
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Patent #:
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Issue Dt:
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03/06/2007
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10268116
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Filing Dt:
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10/08/2002
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Title:
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USE OF ANALOG-VALUED FLOATING-GATE TRANSISTORS FOR PARALLEL AND SERIAL SIGNAL PROCESSING
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Patent #:
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Issue Dt:
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03/23/2004
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Application #:
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10279428
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Filing Dt:
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10/24/2002
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Title:
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SEMICONDUCTOR MEMORY WITH MULTIPLE TIMING LOOPS
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Patent #:
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Issue Dt:
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06/21/2005
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10281384
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Filing Dt:
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10/24/2002
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Title:
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METHOD AND APPARATUS FOR CALIBRATION OF AN ARRAY OF SCALED ELECTRONIC CIRCUIT ELEMENTS
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Patent #:
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Issue Dt:
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09/07/2004
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Application #:
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10295742
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Filing Dt:
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11/15/2002
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Title:
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ELECTRICALLY-ALTERABLE NON-VOLATILE MEMORY CELL
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Patent #:
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01/31/2006
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Application #:
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10313075
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Filing Dt:
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12/06/2002
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Title:
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METHODS AND APPARATUSES FOR TEST CIRCUITRY FOR A DUAL-POLARITY NON-VOLATILE MEMORY CELL
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Patent #:
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Issue Dt:
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10/31/2006
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Application #:
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10313199
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Filing Dt:
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12/06/2002
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Title:
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METHODS AND APPARATUSES FOR A DUAL-POLARITY NON-VOLATILE MEMORY CELL
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Patent #:
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02/17/2009
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10313548
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12/06/2002
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Title:
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PROCESSOR APPARATUS AND METHODS OPTIMIZED FOR CONTROL APPLICATIONS
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Patent #:
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01/11/2005
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10313650
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Filing Dt:
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12/06/2002
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Title:
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METHODS AND APPARATUSES FOR MAINTAINING INFORMATION STORED IN A NON-VOLATILE MEMORY CELL
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Patent #:
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Issue Dt:
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10/02/2007
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10330632
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Filing Dt:
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12/26/2002
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Title:
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METHODS AND APPARATUS FOR COMPILING INSTRUCTIONS FOR A DATA PROCESSOR
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Patent #:
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Issue Dt:
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05/09/2006
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Application #:
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10358495
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Filing Dt:
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02/04/2003
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Title:
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METHOD AND APPARATUS FOR IMPLEMENTING DECODE OPERATIONS IN A DATA PROCESSOR
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Patent #:
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Issue Dt:
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02/21/2006
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Application #:
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10364261
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Filing Dt:
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02/10/2003
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Title:
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METHODS AND APPARATUSES FOR A ROM MEMORY ARRAY HAVING A VIRTUALLY GROUNDED LINE
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Patent #:
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Issue Dt:
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01/15/2008
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10371681
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Filing Dt:
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02/20/2003
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Title:
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SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR INTERRUPT SCHEDULING IN PROCESSING COMMUNICATION
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Patent #:
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Issue Dt:
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05/02/2006
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Application #:
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10371829
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Filing Dt:
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02/20/2003
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Title:
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SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR PROCESSING REFLECTIVE STATE MACHINES
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Patent #:
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01/10/2006
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10371830
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02/20/2003
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Title:
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SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR MEMORY MANAGEMENT FOR DEFINING CLASS LISTS AND NODE LISTS FOR ALLOCATION AND DEALLOCATION OF MEMORY BLOCKS
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Issue Dt:
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02/08/2005
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10377845
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Filing Dt:
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02/28/2003
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Title:
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METHODS AND APPARATUSES FOR A ROM MEMORY ARRAY HAVING TWISTED SOURCE OR BIT LINES
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Patent #:
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Issue Dt:
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01/30/2007
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10420299
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04/21/2003
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11/13/2003
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Title:
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METHOD AND APPARATUS FOR JUMP CONTROL IN A PIPELINED PROCESSOR
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Patent #:
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01/06/2009
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10423745
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04/25/2003
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12/11/2003
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Title:
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APPARATUS AND METHOD FOR MANAGING INTEGRATED CIRCUIT DESIGNS
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10/31/2006
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10425286
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04/28/2003
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Title:
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SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR SHARED MEMORY QUEUE
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Patent #:
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09/27/2005
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10437262
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05/12/2003
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02/26/2004
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Title:
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DIFFERENTIAL FLOATING GATE NONVOLATILE MEMORIES
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Issue Dt:
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10/25/2005
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Application #:
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10447684
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Filing Dt:
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05/28/2003
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Title:
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AUTOZEROING FLOATING-GATE AMPLIFIER
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