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Patent Assignment Details

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Reel/Frame:	025346/0795			Pages:	3
		Recorded:	11/11/2010
Attorney Dkt #:	VARIOUS
Conveyance:	CORRECTION OF NAME AND ADDRESS

Total properties: 18

Patent #:	4675546	Issue Dt:	06/23/1987	Application #:	06893033	Filing Dt:	08/04/1986
Title:	EDGE PROGRAMMABLE TIMING SIGNAL GENERATOR

Patent #:	4980862	Issue Dt:	12/25/1990	Application #:	07268590	Filing Dt:	11/08/1988
Title:	FOLDED BITLINE DYNAMIC RAM WITH REDUCED SHARED SUPPLY VOLTAGES

Patent #:	5148165	Issue Dt:	09/15/1992	Application #:	07451225	Filing Dt:	12/15/1989
Title:	CMOS DIGITAL TO ANALOG SIGNAL CONVERTER CIRCUIT

Patent #:	5042012	Issue Dt:	08/20/1991	Application #:	07497267	Filing Dt:	03/22/1990
Title:	SERIAL ACCESS DYNAMIC RAM

Patent #:	5093808	Issue Dt:	03/03/1992	Application #:	07585714	Filing Dt:	09/19/1990
Title:	FOLDED BITLINE DYNAMIC RAM WITH REDUCED SHARED SUPPLY VOLTAGES

Patent #:	5198708	Issue Dt:	03/30/1993	Application #:	07680745	Filing Dt:	04/05/1991
Title:	TRANSITION DETECTION CIRCUIT

Patent #:	5214602	Issue Dt:	05/25/1993	Application #:	07680746	Filing Dt:	04/05/1991
Title:	DYNAMIC MEMORY WORD LINE DRIVER SCHEME

Patent #:	5255232	Issue Dt:	10/19/1993	Application #:	07680748	Filing Dt:	04/05/1991
Title:	DRAM CELL PLATE AND PRECHARGE VOLTAGE GENERATOR

Patent #:	5233560	Issue Dt:	08/03/1993	Application #:	07680834	Filing Dt:	04/05/1991
Title:	DYNAMIC MEMORY BIT LINE PRECHARGE SCHEME

Patent #:	5245576	Issue Dt:	09/14/1993	Application #:	07680995	Filing Dt:	04/05/1991
Title:	DYNAMIC MEMORY ROW/COLUMN REDUNDANCY SCHEME

Patent #:	5633607	Issue Dt:	05/27/1997	Application #:	08430228	Filing Dt:	04/28/1995
Title:	EDGE TRIGGERED SET-RESET FLIP-FLOP (SRFF)

Patent #:	5777501	Issue Dt:	07/07/1998	Application #:	08638809	Filing Dt:	04/29/1996
Title:	DIGITAL DELAY LINE FOR A REDUCED JITTER DIGITAL DELAY LOCK LOOP

Patent #:	5686848	Issue Dt:	11/11/1997	Application #:	08638810	Filing Dt:	04/29/1996
Title:	POWER-UP/POWER-DOWN RESET CIRCUIT FOR LOW VOLTAGE INTERVAL

Patent #:	5973552	Issue Dt:	10/26/1999	Application #:	08743348	Filing Dt:	11/04/1996
Title:	POWER SAVINGS TECHNIQUE IN SOLID STATE INTEGRATED CIRCUITS

Patent #:	5870049	Issue Dt:	02/09/1999	Application #:	08838168	Filing Dt:	04/16/1997
Title:	CURRENT MODE DIGITAL TO ANALOGUE CONVERTER

Patent #:	5877992	Issue Dt:	03/02/1999	Application #:	09000954	Filing Dt:	12/30/1997
Title:	DATA-BIT REDUNDANCY IN SEMICONDUCTOR MEMORIES

Patent #:	6151260	Issue Dt:	11/21/2000	Application #:	09046636	Filing Dt:	03/24/1998
Title:	METHOD FOR MULTILEVEL DRAM SENSING

Patent #:	6141289	Issue Dt:	10/31/2000	Application #:	09277828	Filing Dt:	03/29/1999
Title:	STRUCTURE OF RANDOM ACCESS MEMORY FORMED OF MULTIBIT CELLS

Assignor

Exec Dt:

09/17/2009

Assignee

11 HINES ROAD

KANATA, CANADA K2K 2X1

Correspondence name and address
	MOSAID TECHNOLOGIES INCORPORATED
	11 HINES ROAD
	SUITE 203
	OTTAWA, K2K 2X1 CANADA

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