Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 025443/0543 | |
| Pages: | 13 |
| | Recorded: | 12/02/2010 | | |
| Attorney Dkt #: | 5649-3123 |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
3
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Patent #:
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Issue Dt:
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01/13/2004
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Application #:
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08871295
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Filing Dt:
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06/09/1997
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Title:
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MICROPROCESSOR CHIP HAVING A MEMORY THAT IS RECONFIGURABLE TO FUNCTION AS ON-CHIP MAIN MEMORY OR AN ON-CHIP CACHE
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Patent #:
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Issue Dt:
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03/27/2001
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Application #:
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09032969
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Filing Dt:
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03/02/1998
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Title:
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INTEGRATED HIERARCHICAL MEMORY OVERLAY METHOD FOR IMPROVED PROCESSOR PERFORMANCE
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Patent #:
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Issue Dt:
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09/27/2005
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Application #:
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10870847
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Filing Dt:
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06/17/2004
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Publication #:
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Pub Dt:
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12/02/2004
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Title:
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MEMORY MANAGER FOR A COMMON MEMORY
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Assignee
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| 416 MAETAN-DONG, YEONGTONG-GU |
| SUWON-SI |
| GYEONGGI-DO, KOREA, REPUBLIC OF |
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Correspondence name and address
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MYERS BIGEL SIBLEY & SAJOVEC, P.A./KSC
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4140 PARKLAKE AVENUE
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SUITE 600
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RALEIGH, NC 27612
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